c729908bac
- Includes following SLE 15 SP5 jira features: * jsc#PED-671 mcelog: Update to latest release * jsc#PED-686 [CPU Features] Update mcelog support for ADL-N * jsc#PED-638 [CPU Features] Update mcelog support for MTL-P - Update to version 189: - Had to adopt to latest CPU identification model mainline patch: b54ee05056a76e mcelog: Drop CASE_INTEL define and friends A add_new_amd_cpu_defines D add-defines.patch M Start-consolidating-AMD-specific-stuff.patch M add-f10h-support.patch M add-f11h-support.patch M add-f12h-support.patch M add-f14h-support.patch M add-f15h-support.patch M add-f16h-support.patch M email.patch M fix_setgroups_missing_call.patch OBS-URL: https://build.opensuse.org/request/show/1092613 OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=104
138 lines
3.0 KiB
Diff
138 lines
3.0 KiB
Diff
Add F14h decoding support
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Signed-off-by: Borislav Petkov <bp@suse.de>
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---
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amd.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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amd.h | 3 +-
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mcelog.c | 2 +
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mcelog.h | 1
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4 files changed, 93 insertions(+), 1 deletion(-)
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Index: mcelog-189/amd.c
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===================================================================
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--- mcelog-189.orig/amd.c
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+++ mcelog-189/amd.c
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@@ -159,6 +159,8 @@ enum cputype select_amd_cputype(u32 fami
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return CPU_F11H;
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case 0x12:
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return CPU_F12H;
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+ case 0x14:
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+ return CPU_F14H;
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default:
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break;
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}
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@@ -381,6 +383,58 @@ static bool k8_mc0_mce(u16 ec, u8 xec)
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return f10h_mc0_mce(ec, xec);
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}
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+static bool cat_mc0_mce(u16 ec, u8 xec)
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+{
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+ u8 r4 = R4(ec);
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+ bool ret = true;
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+
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+ if (MEM_ERROR(ec)) {
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+
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+ if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
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+ return false;
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+
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+ switch (r4) {
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+ case R4_DRD:
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+ case R4_DWR:
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+ Wprintf("Data/Tag parity error due to %s.\n",
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+ (r4 == R4_DRD ? "load/hw prf" : "store"));
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+ break;
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+ case R4_EVICT:
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+ Wprintf("Copyback parity error on a tag miss.\n");
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+ break;
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+ case R4_SNOOP:
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+ Wprintf("Tag parity error during snoop.\n");
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+ break;
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+ default:
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+ ret = false;
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+ }
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+ } else if (BUS_ERROR(ec)) {
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+
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+ if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
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+ return false;
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+
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+ Wprintf("System read data error on a ");
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+
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+ switch (r4) {
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+ case R4_RD:
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+ Wprintf("TLB reload.\n");
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+ break;
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+ case R4_DWR:
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+ Wprintf("store.\n");
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+ break;
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+ case R4_DRD:
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+ Wprintf("load.\n");
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+ break;
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+ default:
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+ ret = false;
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+ }
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+ } else {
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+ ret = false;
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+ }
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+
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+ return ret;
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+}
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+
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static void decode_mc0_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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u16 ec = EC(m->status);
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@@ -402,6 +456,31 @@ static void decode_mc0_mce(struct amd_de
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Eprintf("Corrupted MC0 MCE info?\n");
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}
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+static bool cat_mc1_mce(u16 ec, u8 xec)
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+{
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+ u8 r4 = R4(ec);
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+ bool ret = true;
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+
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+ if (!MEM_ERROR(ec))
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+ return false;
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+
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+ if (TT(ec) != TT_INSTR)
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+ return false;
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+
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+ if (r4 == R4_IRD)
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+ Wprintf("Data/tag array parity error for a tag hit.\n");
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+ else if (r4 == R4_SNOOP)
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+ Wprintf("Tag error during snoop/victimization.\n");
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+ else if (xec == 0x0)
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+ Wprintf("Tag parity error from victim castout.\n");
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+ else if (xec == 0x2)
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+ Wprintf("Microcode patch RAM parity error.\n");
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+ else
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+ ret = false;
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+
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+ return ret;
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+}
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+
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static void decode_mc1_mce(struct amd_decoder_ops *ops, struct mce *m)
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{
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u16 ec = EC(m->status);
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@@ -656,6 +735,12 @@ struct amd_decoder_ops fam_ops[] = {
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.mc1_mce = k8_mc1_mce,
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.mc2_mce = k8_mc2_mce,
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},
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+ [AMD_F14H] = {
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+ .cpu = AMD_F14H,
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+ .mc0_mce = cat_mc0_mce,
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+ .mc1_mce = cat_mc1_mce,
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+ .mc2_mce = k8_mc2_mce,
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+ },
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};
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static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
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@@ -672,6 +757,9 @@ static void __decode_amd_mc(enum cputype
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case CPU_F12H:
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ops = &fam_ops[AMD_F12H];
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break;
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+ case CPU_F14H:
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+ ops = &fam_ops[AMD_F14H];
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+ break;
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default:
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Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
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return;
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