mcelog/add-f16h-support.patch
Thomas Renninger c729908bac Accepting request 1092613 from home:trenn
- Includes following SLE 15 SP5 jira features:
  * jsc#PED-671 mcelog: Update to latest release
  * jsc#PED-686 [CPU Features] Update mcelog support for ADL-N
  * jsc#PED-638 [CPU Features] Update mcelog support for MTL-P
- Update to version 189:
- Had to adopt to latest CPU identification model
  mainline patch:
  b54ee05056a76e mcelog: Drop CASE_INTEL define
  and friends
A    add_new_amd_cpu_defines
D    add-defines.patch
M    Start-consolidating-AMD-specific-stuff.patch
M    add-f10h-support.patch
M    add-f11h-support.patch
M    add-f12h-support.patch
M    add-f14h-support.patch
M    add-f15h-support.patch
M    add-f16h-support.patch
M    email.patch
M    fix_setgroups_missing_call.patch

OBS-URL: https://build.opensuse.org/request/show/1092613
OBS-URL: https://build.opensuse.org/package/show/Base:System/mcelog?expand=0&rev=104
2023-06-12 15:26:55 +00:00

96 lines
2.1 KiB
Diff

Add F16h decoding support
Signed-off-by: Borislav Petkov <bp@suse.de>
---
amd.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
amd.h | 3 ++-
mcelog.c | 2 ++
mcelog.h | 1 +
4 files changed, 58 insertions(+), 1 deletion(-)
Index: mcelog-189/amd.c
===================================================================
--- mcelog-189.orig/amd.c
+++ mcelog-189/amd.c
@@ -200,6 +200,8 @@ enum cputype select_amd_cputype(u32 fami
return CPU_F14H;
case 0x15:
return CPU_F15H;
+ case 0x16:
+ return CPU_F16H;
default:
break;
}
@@ -687,6 +689,47 @@ static bool f15h_mc2_mce(u16 ec, u8 xec)
return ret;
}
+static bool f16h_mc2_mce(u16 ec, u8 xec)
+{
+ u8 r4 = R4(ec);
+
+ if (!MEM_ERROR(ec))
+ return false;
+
+ switch (xec) {
+ case 0x04 ... 0x05:
+ Wprintf("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
+ break;
+
+ case 0x09 ... 0x0b:
+ case 0x0d ... 0x0f:
+ Wprintf("ECC error in L2 tag (%s).\n",
+ ((r4 == R4_GEN) ? "BankReq" :
+ ((r4 == R4_SNOOP) ? "Prb" : "Fill")));
+ break;
+
+ case 0x10 ... 0x19:
+ case 0x1b:
+ Wprintf("ECC error in L2 data array (%s).\n",
+ (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" :
+ ((r4 == R4_GEN) ? "Attr" :
+ ((r4 == R4_EVICT) ? "Vict" : "Fill"))));
+ break;
+
+ case 0x1c ... 0x1d:
+ case 0x1f:
+ Wprintf("Parity error in L2 attribute bits (%s).\n",
+ ((r4 == R4_RD) ? "Hit" :
+ ((r4 == R4_GEN) ? "Attr" : "Fill")));
+ break;
+
+ default:
+ return false;
+ }
+
+ return true;
+}
+
static void decode_mc2_mce(struct amd_decoder_ops *ops, struct mce *m)
{
u16 ec = EC(m->status);
@@ -897,6 +940,12 @@ struct amd_decoder_ops fam_ops[] = {
.mc1_mce = f15h_mc1_mce,
.mc2_mce = f15h_mc2_mce,
},
+ [AMD_F16H] = {
+ .cpu = AMD_F16H,
+ .mc0_mce = cat_mc0_mce,
+ .mc1_mce = cat_mc1_mce,
+ .mc2_mce = f16h_mc2_mce,
+ },
};
static void __decode_amd_mc(enum cputype cpu, struct mce *mce)
@@ -920,6 +969,10 @@ static void __decode_amd_mc(enum cputype
xec_mask = 0x1f;
ops = &fam_ops[AMD_F15H];
break;
+ case CPU_F16H:
+ xec_mask = 0x1f;
+ ops = &fam_ops[AMD_F16H];
+ break;
default:
Eprintf("Huh? What family is it: 0x%x?!\n", cpu);
return;