5914ab837d
- Add 2 upstream bug fixes for Silk:
* opus-Silk-CNG-adapts-faster.patch: Silk CNG adapts faster to
received packets with lower gains.
* opus-Silk-fix-arm-optimization.patch: Avoid processing LPC
coeffs beyond the given order in NEON optimizations.
OBS-URL: https://build.opensuse.org/request/show/723806
OBS-URL: https://build.opensuse.org/package/show/multimedia:libs/opus?expand=0&rev=41
88 lines
4.1 KiB
Diff
88 lines
4.1 KiB
Diff
From 812ae3fb5c589aaafe761b8ebf86bcbbb8f0ed76 Mon Sep 17 00:00:00 2001
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From: Felicia Lim <flim@google.com>
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Date: Mon, 8 Jul 2019 09:44:35 -0700
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Subject: [PATCH] Avoid processing LPC coeffs beyond the given order in NEON
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optimizations
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---
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silk/arm/LPC_inv_pred_gain_neon_intr.c | 22 +++++++++++++++-------
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1 file changed, 15 insertions(+), 7 deletions(-)
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diff --git a/silk/arm/LPC_inv_pred_gain_neon_intr.c b/silk/arm/LPC_inv_pred_gain_neon_intr.c
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index ab426bcd..726e6667 100644
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--- a/silk/arm/LPC_inv_pred_gain_neon_intr.c
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+++ b/silk/arm/LPC_inv_pred_gain_neon_intr.c
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@@ -210,19 +210,23 @@ opus_int32 silk_LPC_inverse_pred_gain_neon( /* O Returns inverse predi
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/* Increase Q domain of the AR coefficients */
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t0_s16x8 = vld1q_s16( A_Q12 + 0 );
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t1_s16x8 = vld1q_s16( A_Q12 + 8 );
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- t2_s16x8 = vld1q_s16( A_Q12 + 16 );
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+ if ( order > 16 ) {
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+ t2_s16x8 = vld1q_s16( A_Q12 + 16 );
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+ }
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t0_s32x4 = vpaddlq_s16( t0_s16x8 );
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switch( order - leftover )
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{
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case 24:
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t0_s32x4 = vpadalq_s16( t0_s32x4, t2_s16x8 );
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+ vst1q_s32( Atmp_QA + 16, vshll_n_s16( vget_low_s16 ( t2_s16x8 ), QA - 12 ) );
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+ vst1q_s32( Atmp_QA + 20, vshll_n_s16( vget_high_s16( t2_s16x8 ), QA - 12 ) );
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/* FALLTHROUGH */
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case 16:
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t0_s32x4 = vpadalq_s16( t0_s32x4, t1_s16x8 );
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- vst1q_s32( Atmp_QA + 16, vshll_n_s16( vget_low_s16 ( t2_s16x8 ), QA - 12 ) );
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- vst1q_s32( Atmp_QA + 20, vshll_n_s16( vget_high_s16( t2_s16x8 ), QA - 12 ) );
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+ vst1q_s32( Atmp_QA + 8, vshll_n_s16( vget_low_s16 ( t1_s16x8 ), QA - 12 ) );
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+ vst1q_s32( Atmp_QA + 12, vshll_n_s16( vget_high_s16( t1_s16x8 ), QA - 12 ) );
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/* FALLTHROUGH */
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case 8:
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@@ -230,8 +234,8 @@ opus_int32 silk_LPC_inverse_pred_gain_neon( /* O Returns inverse predi
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const int32x2_t t_s32x2 = vpadd_s32( vget_low_s32( t0_s32x4 ), vget_high_s32( t0_s32x4 ) );
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const int64x1_t t_s64x1 = vpaddl_s32( t_s32x2 );
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DC_resp = vget_lane_s32( vreinterpret_s32_s64( t_s64x1 ), 0 );
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- vst1q_s32( Atmp_QA + 8, vshll_n_s16( vget_low_s16 ( t1_s16x8 ), QA - 12 ) );
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- vst1q_s32( Atmp_QA + 12, vshll_n_s16( vget_high_s16( t1_s16x8 ), QA - 12 ) );
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+ vst1q_s32( Atmp_QA + 0, vshll_n_s16( vget_low_s16 ( t0_s16x8 ), QA - 12 ) );
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+ vst1q_s32( Atmp_QA + 4, vshll_n_s16( vget_high_s16( t0_s16x8 ), QA - 12 ) );
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}
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break;
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@@ -246,16 +250,22 @@ opus_int32 silk_LPC_inverse_pred_gain_neon( /* O Returns inverse predi
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case 6:
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DC_resp += (opus_int32)A_Q12[ 5 ];
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DC_resp += (opus_int32)A_Q12[ 4 ];
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+ Atmp_QA[ order - leftover + 5 ] = silk_LSHIFT32( (opus_int32)A_Q12[ 5 ], QA - 12 );
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+ Atmp_QA[ order - leftover + 4 ] = silk_LSHIFT32( (opus_int32)A_Q12[ 4 ], QA - 12 );
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/* FALLTHROUGH */
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case 4:
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DC_resp += (opus_int32)A_Q12[ 3 ];
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DC_resp += (opus_int32)A_Q12[ 2 ];
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+ Atmp_QA[ order - leftover + 3 ] = silk_LSHIFT32( (opus_int32)A_Q12[ 3 ], QA - 12 );
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+ Atmp_QA[ order - leftover + 2 ] = silk_LSHIFT32( (opus_int32)A_Q12[ 2 ], QA - 12 );
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/* FALLTHROUGH */
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case 2:
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DC_resp += (opus_int32)A_Q12[ 1 ];
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DC_resp += (opus_int32)A_Q12[ 0 ];
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+ Atmp_QA[ order - leftover + 1 ] = silk_LSHIFT32( (opus_int32)A_Q12[ 1 ], QA - 12 );
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+ Atmp_QA[ order - leftover + 0 ] = silk_LSHIFT32( (opus_int32)A_Q12[ 0 ], QA - 12 );
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/* FALLTHROUGH */
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default:
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@@ -266,8 +276,6 @@ opus_int32 silk_LPC_inverse_pred_gain_neon( /* O Returns inverse predi
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if( DC_resp >= 4096 ) {
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invGain_Q30 = 0;
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} else {
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- vst1q_s32( Atmp_QA + 0, vshll_n_s16( vget_low_s16 ( t0_s16x8 ), QA - 12 ) );
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- vst1q_s32( Atmp_QA + 4, vshll_n_s16( vget_high_s16( t0_s16x8 ), QA - 12 ) );
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invGain_Q30 = LPC_inverse_pred_gain_QA_neon( Atmp_QA, order );
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}
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}
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--
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2.11.0
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