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a6d65a69fa |
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microcode-20250812.tar.gz
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microcode-20250812.tar.gz
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microcode-20260210.tar.gz
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microcode-20260210.tar.gz
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@@ -1,3 +1,95 @@
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-------------------------------------------------------------------
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Wed Feb 11 13:10:01 UTC 2026 - Marcus Meissner <meissner@suse.com>
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- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046)
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- CVE-2024-24853: Updated fix for incorrect behavior order in transition
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between executive monitor and SMI transfer monitor (STM) in some Intel(R)
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Processor may allow a privileged user to potentially enable escalation
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of privilege via local access. (bsc#1229129)
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- CVE-2025-31648: Improper handling of values in the
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microcode flow for some Intel Processor Family may allow
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an escalation of privilege. (bsc#1258046 INTEL-SA-01396
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https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01396.html)
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- Update for various functional issues.
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- Updated Platforms:
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| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
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|:---------------|:---------|:------------|:---------|:---------|:---------
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| ADL | C0 | 06-97-02/07 | 0000003d | 0000003e | Core Gen12
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| ADL | H0 | 06-97-05/07 | 0000003d | 0000003e | Core Gen12
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| ADL | L0 | 06-9a-03/80 | 0000043a | 0000043b | Core Gen12
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| ADL | R0 | 06-9a-04/80 | 0000043a | 0000043b | Core Gen12
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| ADL-N | N0 | 06-be-00/19 | 0000001e | 00000021 | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
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| ARL-H | A1 | 06-c5-02/82 | 0000011a | 0000011b | Core Ultra Processor (Series 2)
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| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 0000011a | 0000011b | Core Ultra Processor (Series 2)
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| ARL-U | A0 | 06-b5-00/80 | 0000000a | 0000000d | Core Ultra Processor (Series 2)
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| AZB | A0/R0 | 06-9a-04/40 | 0000000b | 0000000c | Atom C1100
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| EMR-SP | A1 | 06-cf-02/87 | 210002c0 | 210002d3 | Xeon Scalable Gen5
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| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 010003f0 | 01000405 | Xeon 6900/6700/6500 Series Processors with P-Cores
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| GNR-D | B0/B1 | 06-ae-01/97 | 01000273 | 010002f3 | Xeon 6700P-B/6500P-B Series SoC with P-Cores
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| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000124 | 0a000133 | Xeon 6700/6500-Series Processors with P-Cores
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| ICL-D | B0 | 06-6c-01/10 | 010002e0 | 010002f1 | Xeon D-17xx, D-27xx
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| ICL-U/Y | D1 | 06-7e-05/80 | 000000ca | 000000cc | Core Gen10 Mobile
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| ICX-SP | Dx/M1 | 06-6a-06/87 | 0d000410 | 0d000421 | Xeon Scalable Gen3
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| MTL | C0 | 06-aa-04/e6 | 00000025 | 00000028 | Core Ultra Processor
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| RKL-S | B0 | 06-a7-01/02 | 00000064 | 00000065 | Core Gen11
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| RPL-E/HX/S | B0 | 06-b7-01/32 | 00000132 | 00000133 | Core Gen13/Gen14
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| RPL-H/P/PX 6+8 | J0 | 06-ba-02/e0 | 00006133 | 00006134 | Core Gen13
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| RPL-HX/S | C0 | 06-bf-02/07 | 0000003d | 0000003e | Core Gen13/Gen14
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| RPL-S | H0 | 06-bf-05/07 | 0000003d | 0000003e | Core Gen13/Gen14
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| RPL-U 2+8 | Q0 | 06-ba-03/e0 | 00006133 | 00006134 | Core Gen13
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| SPR-HBM | Bx | 06-8f-08/10 | 2c000410 | 2c000421 | Xeon Max
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| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000650 | 2b000661 | Xeon Scalable Gen4
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| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000650 | 2b000661 | Xeon Scalable Gen4
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| TGL | B0/B1 | 06-8c-01/80 | 000000bc | 000000be | Core Gen11 Mobile
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| TGL-H | R0 | 06-8d-01/c2 | 00000056 | 00000058 | Core Gen11 Mobile
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| TGL-R | C0 | 06-8c-02/c2 | 0000003c | 0000003e | Core Gen11 Mobile
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| TWL | N0 | 06-be-00/19 | 0000001e | 00000021 | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
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-------------------------------------------------------------------
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Wed Nov 12 13:15:59 UTC 2025 - Marcus Meissner <meissner@suse.com>
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- Intel CPU Microcode was updated to the 20251111 release (bsc#1253319)
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- Update for functional issues.
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New Platforms:
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| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
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|:---------------|:---------|:------------|:---------|:---------|:---------
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| GNR-D | B0/B1 | 06-ae-01/97 | | 01000273 | Xeon 6700P-B/6500P-B Series SoC with P-Cores
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Updated Platforms:
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| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
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|:---------------|:---------|:------------|:---------|:---------|:---------
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| ADL | C0 | 06-97-02/07 | 0000003a | 0000003d | Core Gen12
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| ADL | H0 | 06-97-05/07 | 0000003a | 0000003d | Core Gen12
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| ADL | L0 | 06-9a-03/80 | 00000437 | 0000043a | Core Gen12
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| ADL | R0 | 06-9a-04/80 | 00000437 | 0000043a | Core Gen12
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| ADL-N | N0 | 06-be-00/19 | 0000001d | 0000001e | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
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| ARL-H | A1 | 06-c5-02/82 | 00000119 | 0000011a | Core Ultra Processor (Series 2)
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| ARL-S/HX (8P) | B0 | 06-c6-02/82 | 00000119 | 0000011a | Core Ultra Processor (Series 2)
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| AZB | A0/R0 | 06-9a-04/40 | 0000000a | 0000000b | Atom C1100
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| EMR-SP | A1 | 06-cf-02/87 | 210002b3 | 210002c0 | Xeon Scalable Gen5
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| GNR-AP/SP | Bx/Hx/Lx | 06-ad-01/95 | 010003d0 | 010003f0 | Xeon 6900-6700/6500-Series Processors with P-Cores
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| GNR-SP R1S | Bx/Hx/Lx | 06-ad-01/20 | 0a000100 | 0a000124 | Xeon 6700/6500-Series Processors with P-Cores
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| LNL | B0 | 06-bd-01/80 | 00000123 | 00000125 | Core Ultra 200 V Series Processor
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| RPL-E/HX/S | B0 | 06-b7-01/32 | 0000012f | 00000132 | Core Gen13/Gen14
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| RPL-H/P/PX 6+8 | J0 | 06-ba-02/e0 | 00004129 | 00006133 | Core Gen13
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| RPL-HX/S | C0 | 06-bf-02/07 | 0000003a | 0000003d | Core Gen13/Gen14
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| RPL-S | H0 | 06-bf-05/07 | 0000003a | 0000003d | Core Gen13/Gen14
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| RPL-U 2+8 | Q0 | 06-ba-03/e0 | 00004129 | 00006133 | Core Gen13
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| SPR-HBM | Bx | 06-8f-08/10 | 2c000401 | 2c000410 | Xeon Max
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| SPR-SP | E4/S2 | 06-8f-07/87 | 2b000643 | 2b000650 | Xeon Scalable Gen4
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| SPR-SP | E5/S3 | 06-8f-08/87 | 2b000643 | 2b000650 | Xeon Scalable Gen4
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| SRF-AP/SP | C0 | 06-af-03/01 | 03000362 | 03000382 | Xeon 6900/6700-Series Processors with E-Cores
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| TWL | N0 | 06-be-00/19 | 0000001d | 0000001e | Core i3-N305/N300, N50/N97/N100/N200, Atom x7211E/x7213E/x7425E
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-------------------------------------------------------------------
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Mon Sep 22 14:15:14 UTC 2025 - Marcus Meissner <meissner@suse.com>
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- switch the supplements to use supplements + kernel to allow
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moving a installation to Intel hardware (bsc#1249138)
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-------------------------------------------------------------------
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Thu Aug 21 10:32:02 UTC 2025 - Marcus Meissner <meissner@suse.com>
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@@ -278,12 +370,11 @@ Wed Nov 13 10:50:31 UTC 2024 - Marcus Meissner <meissner@suse.com>
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-------------------------------------------------------------------
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Thu Oct 31 13:27:15 UTC 2024 - Marcus Meissner <meissner@suse.com>
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- Intel CPU Microcode was updated to the 20241029 release
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- Intel CPU Microcode was updated to the 20241029 release (bsc#1230400)
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Update for functional issues. Refer to [14th/13th Generation Intel Core Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details.
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Update for functional issues. Refer to [14th/13th Generation Intel® Core™ Processor Specification Update](https://cdrdv2.intel.com/v1/dl/getContent/740518) for details.
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Updated Platforms:
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| Processor | Stepping | F-M-S/PI | Old Ver | New Ver | Products
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|:---------------|:---------|:------------|:---------|:---------|:---------
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| RPL-E/HX/S | B0 | 06-b7-01/32 | 00000129 | 0000012b | Core Gen13/Gen14
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@@ -1,7 +1,7 @@
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#
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# spec file for package ucode-intel
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#
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# Copyright (c) 2024 SUSE LLC
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# Copyright (c) 2026 SUSE LLC and contributors
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#
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# All modifications and additions to the file contributed by third parties
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# remain the property of their copyright owners, unless otherwise agreed
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@@ -20,7 +20,7 @@
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%define _firmwaredir /lib/firmware
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%endif
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Name: ucode-intel
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Version: 20250812
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Version: 20260210
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Release: 0
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Summary: Microcode Updates for Intel x86/x86-64 CPUs
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License: SUSE-Firmware
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@@ -30,12 +30,12 @@ BuildRequires: suse-module-tools
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URL: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files
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Source0: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/archive/microcode-%version.tar.gz
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Source1: ucode-intel-rpmlintrc
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Supplements: modalias(x86cpu:vendor%3A0000%3Afamily%3A*%3Amodel%3A*%3Afeature%3A*)
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Supplements: (modalias(x86cpu:vendor%3A0000%3Afamily%3A*%3Amodel%3A*%3Afeature%3A*) and kernel)
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# new method ... note that only 1 : might be present, otherwise libzypp misinterprets it.
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Supplements: modalias(cpu:type%3Ax86*ven0000*)
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Supplements: (modalias(cpu:type%3Ax86*ven0000*) and kernel)
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BuildRoot: %{_tmppath}/%{name}-%{version}-build
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Requires(post): coreutils
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Requires(postun):coreutils
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Requires(postun): coreutils
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ExclusiveArch: %ix86 x86_64
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%description
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Reference in New Issue
Block a user