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- update to 3.15.0 (fate#327402):

Browse Source 
3.15.0 is a feature release with many improvements and the usual collection of
  bug fixes.
  This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,
  PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux,
  MIPS64/Linux, ARM/Android, ARM64/Android, MIPS32/Android, X86/Android,
  X86/Solaris, AMD64/Solaris and AMD64/MacOSX 10.12.  There is also preliminary
  support for X86/macOS 10.13 and AMD64/macOS 10.13.
  * ==================== CORE CHANGES ===================
  * The XTree Massif output format now makes use of the information obtained
  when specifying --read-inline-info=yes.
  * amd64 (x86_64): the RDRAND and F16C insn set extensions are now supported.
  * ==================== TOOL CHANGES ====================
  * DHAT:
  - DHAT been thoroughly overhauled, improved, and given a GUI.  As a result,
    it has been promoted from an experimental tool to a regular tool.  Run it
    with --tool=dhat instead of --tool=exp-dhat.
  - DHAT now prints only minimal data when the program ends, instead writing
    the bulk of the profiling data to a file.  As a result, the --show-top-n
    and --sort-by options have been removed.
  - Profile results can be viewed with the new viewer, dh_view.html.  When
    a run ends, a short message is printed, explaining how to view the result.
  - See the documentation for more details.
  * Cachegrind:
  - cg_annotate has a new option, --show-percs, which prints percentages next
    to all event counts.
  * Callgrind:
  - callgrind_annotate has a new option, --show-percs, which prints percentages
    next to all event counts.
  - callgrind_annotate now inserts commas in call counts, and

OBS-URL: https://build.opensuse.org/package/show/devel:tools/valgrind?expand=0&rev=197
This commit is contained in:
Dirk Mueller 2019-05-08 15:38:55 +00:00 committed by Git OBS Bridge
parent e60ce74b2a
commit d2d9c242a7
14 changed files with 83 additions and 5311 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1626
0001-Bug-385411-s390x-Add-z13-vector-floating-point-suppo.patch
View File

File diff suppressed because it is too large Load Diff

2339
0001-Bug-385411-s390x-Tests-and-internals-for-z13-vector-.patch
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File diff suppressed because it is too large Load Diff

402
0001-Bug-397187-s390x-Add-vector-register-support-for-vgd.patch
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@ -1,402 +0,0 @@
From 50bd2282bce101012a5668b670cb185375600d2d Mon Sep 17 00:00:00 2001
From: Andreas Arnez <arnez@linux.ibm.com>
Date: Thu, 18 Oct 2018 17:51:57 +0200
Subject: [PATCH] Bug 397187 s390x: Add vector register support for vgdb
On s390x machines with a vector facility, Valgrind's gdbserver didn't
represent the vector registers. This is fixed.
---
NEWS | 1 +
coregrind/Makefile.am | 5 +
coregrind/m_gdbserver/s390-vx-valgrind-s1.xml | 43 ++++++++
coregrind/m_gdbserver/s390-vx-valgrind-s2.xml | 43 ++++++++
coregrind/m_gdbserver/s390-vx.xml | 59 +++++++++++
.../m_gdbserver/s390x-vx-linux-valgrind.xml | 28 ++++++
coregrind/m_gdbserver/s390x-vx-linux.xml | 18 ++++
coregrind/m_gdbserver/valgrind-low-s390x.c | 97 +++++++++++++++++--
8 files changed, 288 insertions(+), 6 deletions(-)
create mode 100644 coregrind/m_gdbserver/s390-vx-valgrind-s1.xml
create mode 100644 coregrind/m_gdbserver/s390-vx-valgrind-s2.xml
create mode 100644 coregrind/m_gdbserver/s390-vx.xml
create mode 100644 coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml
create mode 100644 coregrind/m_gdbserver/s390x-vx-linux.xml
Index: valgrind-3.14.0/coregrind/Makefile.am
===================================================================
--- valgrind-3.14.0.orig/coregrind/Makefile.am
+++ valgrind-3.14.0/coregrind/Makefile.am
@@ -681,6 +681,11 @@ GDBSERVER_XML_FILES = \
m_gdbserver/s390x-linux64-valgrind-s1.xml \
m_gdbserver/s390x-linux64-valgrind-s2.xml \
m_gdbserver/s390x-linux64.xml \
+ m_gdbserver/s390-vx-valgrind-s1.xml \
+ m_gdbserver/s390-vx-valgrind-s2.xml \
+ m_gdbserver/s390-vx.xml \
+ m_gdbserver/s390x-vx-linux-valgrind.xml \
+ m_gdbserver/s390x-vx-linux.xml \
m_gdbserver/mips-cp0-valgrind-s1.xml \
m_gdbserver/mips-cp0-valgrind-s2.xml \
m_gdbserver/mips-cp0.xml \
Index: valgrind-3.14.0/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml
===================================================================
--- /dev/null
+++ valgrind-3.14.0/coregrind/m_gdbserver/s390-vx-valgrind-s1.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.vx-valgrind-s1">
+ <reg name="v0ls1" bitsize="64" type="uint64"/>
+ <reg name="v1ls1" bitsize="64" type="uint64"/>
+ <reg name="v2ls1" bitsize="64" type="uint64"/>
+ <reg name="v3ls1" bitsize="64" type="uint64"/>
+ <reg name="v4ls1" bitsize="64" type="uint64"/>
+ <reg name="v5ls1" bitsize="64" type="uint64"/>
+ <reg name="v6ls1" bitsize="64" type="uint64"/>
+ <reg name="v7ls1" bitsize="64" type="uint64"/>
+ <reg name="v8ls1" bitsize="64" type="uint64"/>
+ <reg name="v9ls1" bitsize="64" type="uint64"/>
+ <reg name="v10ls1" bitsize="64" type="uint64"/>
+ <reg name="v11ls1" bitsize="64" type="uint64"/>
+ <reg name="v12ls1" bitsize="64" type="uint64"/>
+ <reg name="v13ls1" bitsize="64" type="uint64"/>
+ <reg name="v14ls1" bitsize="64" type="uint64"/>
+ <reg name="v15ls1" bitsize="64" type="uint64"/>
+
+ <reg name="v16s1" bitsize="128" type="uint128"/>
+ <reg name="v17s1" bitsize="128" type="uint128"/>
+ <reg name="v18s1" bitsize="128" type="uint128"/>
+ <reg name="v19s1" bitsize="128" type="uint128"/>
+ <reg name="v20s1" bitsize="128" type="uint128"/>
+ <reg name="v21s1" bitsize="128" type="uint128"/>
+ <reg name="v22s1" bitsize="128" type="uint128"/>
+ <reg name="v23s1" bitsize="128" type="uint128"/>
+ <reg name="v24s1" bitsize="128" type="uint128"/>
+ <reg name="v25s1" bitsize="128" type="uint128"/>
+ <reg name="v26s1" bitsize="128" type="uint128"/>
+ <reg name="v27s1" bitsize="128" type="uint128"/>
+ <reg name="v28s1" bitsize="128" type="uint128"/>
+ <reg name="v29s1" bitsize="128" type="uint128"/>
+ <reg name="v30s1" bitsize="128" type="uint128"/>
+ <reg name="v31s1" bitsize="128" type="uint128"/>
+</feature>
Index: valgrind-3.14.0/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml
===================================================================
--- /dev/null
+++ valgrind-3.14.0/coregrind/m_gdbserver/s390-vx-valgrind-s2.xml
@@ -0,0 +1,43 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.vx-valgrind-s2">
+ <reg name="v0ls2" bitsize="64" type="uint64"/>
+ <reg name="v1ls2" bitsize="64" type="uint64"/>
+ <reg name="v2ls2" bitsize="64" type="uint64"/>
+ <reg name="v3ls2" bitsize="64" type="uint64"/>
+ <reg name="v4ls2" bitsize="64" type="uint64"/>
+ <reg name="v5ls2" bitsize="64" type="uint64"/>
+ <reg name="v6ls2" bitsize="64" type="uint64"/>
+ <reg name="v7ls2" bitsize="64" type="uint64"/>
+ <reg name="v8ls2" bitsize="64" type="uint64"/>
+ <reg name="v9ls2" bitsize="64" type="uint64"/>
+ <reg name="v10ls2" bitsize="64" type="uint64"/>
+ <reg name="v11ls2" bitsize="64" type="uint64"/>
+ <reg name="v12ls2" bitsize="64" type="uint64"/>
+ <reg name="v13ls2" bitsize="64" type="uint64"/>
+ <reg name="v14ls2" bitsize="64" type="uint64"/>
+ <reg name="v15ls2" bitsize="64" type="uint64"/>
+
+ <reg name="v16s2" bitsize="128" type="uint128"/>
+ <reg name="v17s2" bitsize="128" type="uint128"/>
+ <reg name="v18s2" bitsize="128" type="uint128"/>
+ <reg name="v19s2" bitsize="128" type="uint128"/>
+ <reg name="v20s2" bitsize="128" type="uint128"/>
+ <reg name="v21s2" bitsize="128" type="uint128"/>
+ <reg name="v22s2" bitsize="128" type="uint128"/>
+ <reg name="v23s2" bitsize="128" type="uint128"/>
+ <reg name="v24s2" bitsize="128" type="uint128"/>
+ <reg name="v25s2" bitsize="128" type="uint128"/>
+ <reg name="v26s2" bitsize="128" type="uint128"/>
+ <reg name="v27s2" bitsize="128" type="uint128"/>
+ <reg name="v28s2" bitsize="128" type="uint128"/>
+ <reg name="v29s2" bitsize="128" type="uint128"/>
+ <reg name="v30s2" bitsize="128" type="uint128"/>
+ <reg name="v31s2" bitsize="128" type="uint128"/>
+</feature>
Index: valgrind-3.14.0/coregrind/m_gdbserver/s390-vx.xml
===================================================================
--- /dev/null
+++ valgrind-3.14.0/coregrind/m_gdbserver/s390-vx.xml
@@ -0,0 +1,59 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2015-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.s390.vx">
+ <vector id="v4f" type="ieee_single" count="4"/>
+ <vector id="v2d" type="ieee_double" count="2"/>
+ <vector id="v16i8" type="int8" count="16"/>
+ <vector id="v8i16" type="int16" count="8"/>
+ <vector id="v4i32" type="int32" count="4"/>
+ <vector id="v2i64" type="int64" count="2"/>
+ <union id="vec128">
+ <field name="v4_float" type="v4f"/>
+ <field name="v2_double" type="v2d"/>
+ <field name="v16_int8" type="v16i8"/>
+ <field name="v8_int16" type="v8i16"/>
+ <field name="v4_int32" type="v4i32"/>
+ <field name="v2_int64" type="v2i64"/>
+ <field name="uint128" type="uint128"/>
+ </union>
+
+ <reg name="v0l" bitsize="64" type="uint64"/>
+ <reg name="v1l" bitsize="64" type="uint64"/>
+ <reg name="v2l" bitsize="64" type="uint64"/>
+ <reg name="v3l" bitsize="64" type="uint64"/>
+ <reg name="v4l" bitsize="64" type="uint64"/>
+ <reg name="v5l" bitsize="64" type="uint64"/>
+ <reg name="v6l" bitsize="64" type="uint64"/>
+ <reg name="v7l" bitsize="64" type="uint64"/>
+ <reg name="v8l" bitsize="64" type="uint64"/>
+ <reg name="v9l" bitsize="64" type="uint64"/>
+ <reg name="v10l" bitsize="64" type="uint64"/>
+ <reg name="v11l" bitsize="64" type="uint64"/>
+ <reg name="v12l" bitsize="64" type="uint64"/>
+ <reg name="v13l" bitsize="64" type="uint64"/>
+ <reg name="v14l" bitsize="64" type="uint64"/>
+ <reg name="v15l" bitsize="64" type="uint64"/>
+
+ <reg name="v16" bitsize="128" type="vec128"/>
+ <reg name="v17" bitsize="128" type="vec128"/>
+ <reg name="v18" bitsize="128" type="vec128"/>
+ <reg name="v19" bitsize="128" type="vec128"/>
+ <reg name="v20" bitsize="128" type="vec128"/>
+ <reg name="v21" bitsize="128" type="vec128"/>
+ <reg name="v22" bitsize="128" type="vec128"/>
+ <reg name="v23" bitsize="128" type="vec128"/>
+ <reg name="v24" bitsize="128" type="vec128"/>
+ <reg name="v25" bitsize="128" type="vec128"/>
+ <reg name="v26" bitsize="128" type="vec128"/>
+ <reg name="v27" bitsize="128" type="vec128"/>
+ <reg name="v28" bitsize="128" type="vec128"/>
+ <reg name="v29" bitsize="128" type="vec128"/>
+ <reg name="v30" bitsize="128" type="vec128"/>
+ <reg name="v31" bitsize="128" type="vec128"/>
+</feature>
Index: valgrind-3.14.0/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml
===================================================================
--- /dev/null
+++ valgrind-3.14.0/coregrind/m_gdbserver/s390x-vx-linux-valgrind.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- S/390 64-bit user-level code. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>s390:64-bit</architecture>
+ <xi:include href="s390x-core64.xml"/>
+ <xi:include href="s390-acr.xml"/>
+ <xi:include href="s390-fpr.xml"/>
+ <xi:include href="s390x-linux64.xml"/>
+ <xi:include href="s390-vx.xml"/>
+ <xi:include href="s390x-core64-valgrind-s1.xml"/>
+ <xi:include href="s390-acr-valgrind-s1.xml"/>
+ <xi:include href="s390-fpr-valgrind-s1.xml"/>
+ <xi:include href="s390x-linux64-valgrind-s1.xml"/>
+ <xi:include href="s390-vx-valgrind-s1.xml"/>
+ <xi:include href="s390x-core64-valgrind-s2.xml"/>
+ <xi:include href="s390-acr-valgrind-s2.xml"/>
+ <xi:include href="s390-fpr-valgrind-s2.xml"/>
+ <xi:include href="s390x-linux64-valgrind-s2.xml"/>
+ <xi:include href="s390-vx-valgrind-s2.xml"/>
+</target>
Index: valgrind-3.14.0/coregrind/m_gdbserver/s390x-vx-linux.xml
===================================================================
--- /dev/null
+++ valgrind-3.14.0/coregrind/m_gdbserver/s390x-vx-linux.xml
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2010-2018 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- S/390 64-bit user-level code. -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+ <architecture>s390:64-bit</architecture>
+ <xi:include href="s390x-core64.xml"/>
+ <xi:include href="s390-acr.xml"/>
+ <xi:include href="s390-fpr.xml"/>
+ <xi:include href="s390x-linux64.xml"/>
+ <xi:include href="s390-vx.xml"/>
+</target>
Index: valgrind-3.14.0/coregrind/m_gdbserver/valgrind-low-s390x.c
===================================================================
--- valgrind-3.14.0.orig/coregrind/m_gdbserver/valgrind-low-s390x.c
+++ valgrind-3.14.0/coregrind/m_gdbserver/valgrind-low-s390x.c
@@ -88,9 +88,42 @@ static struct reg regs[] = {
{ "f14", 2592, 64 },
{ "f15", 2656, 64 },
{ "orig_r2", 2720, 64 },
+ { "v0l", 2784, 64 },
+ { "v1l", 2848, 64 },
+ { "v2l", 2912, 64 },
+ { "v3l", 2976, 64 },
+ { "v4l", 3040, 64 },
+ { "v5l", 3104, 64 },
+ { "v6l", 3168, 64 },
+ { "v7l", 3232, 64 },
+ { "v8l", 3296, 64 },
+ { "v9l", 3360, 64 },
+ { "v10l", 3424, 64 },
+ { "v11l", 3488, 64 },
+ { "v12l", 3552, 64 },
+ { "v13l", 3616, 64 },
+ { "v14l", 3680, 64 },
+ { "v15l", 3744, 64 },
+ { "v16", 3808, 128 },
+ { "v17", 3936, 128 },
+ { "v18", 4064, 128 },
+ { "v19", 4192, 128 },
+ { "v20", 4320, 128 },
+ { "v21", 4448, 128 },
+ { "v22", 4576, 128 },
+ { "v23", 4704, 128 },
+ { "v24", 4832, 128 },
+ { "v25", 4960, 128 },
+ { "v26", 5088, 128 },
+ { "v27", 5216, 128 },
+ { "v28", 5344, 128 },
+ { "v29", 5472, 128 },
+ { "v30", 5600, 128 },
+ { "v31", 5728, 128 },
};
static const char *expedite_regs[] = { "r14", "r15", "pswa", 0 };
-#define num_regs (sizeof (regs) / sizeof (regs[0]))
+#define num_regs_all (sizeof (regs) / sizeof (regs[0]))
+static int num_regs;
static
CORE_ADDR get_pc (void)
@@ -165,7 +198,7 @@ void transfer_register (ThreadId tid, in
case 32: VG_(transfer) (&s390x->guest_a14, buf, dir, size, mod); break;
case 33: VG_(transfer) (&s390x->guest_a15, buf, dir, size, mod); break;
case 34: VG_(transfer) (&s390x->guest_fpc, buf, dir, size, mod); break;
- case 35: VG_(transfer) (&s390x->guest_v0, buf, dir, size, mod); break;
+ case 35: VG_(transfer) (&s390x->guest_v0.w64[0], buf, dir, size, mod); break;
case 36: VG_(transfer) (&s390x->guest_v1.w64[0], buf, dir, size, mod); break;
case 37: VG_(transfer) (&s390x->guest_v2.w64[0], buf, dir, size, mod); break;
case 38: VG_(transfer) (&s390x->guest_v3.w64[0], buf, dir, size, mod); break;
@@ -182,18 +215,65 @@ void transfer_register (ThreadId tid, in
case 49: VG_(transfer) (&s390x->guest_v14.w64[0], buf, dir, size, mod); break;
case 50: VG_(transfer) (&s390x->guest_v15.w64[0], buf, dir, size, mod); break;
case 51: *mod = False; break; //GDBTD??? { "orig_r2", 0, 64 },
+ case 52: VG_(transfer) (&s390x->guest_v0.w64[1], buf, dir, size, mod); break;
+ case 53: VG_(transfer) (&s390x->guest_v1.w64[1], buf, dir, size, mod); break;
+ case 54: VG_(transfer) (&s390x->guest_v2.w64[1], buf, dir, size, mod); break;
+ case 55: VG_(transfer) (&s390x->guest_v3.w64[1], buf, dir, size, mod); break;
+ case 56: VG_(transfer) (&s390x->guest_v4.w64[1], buf, dir, size, mod); break;
+ case 57: VG_(transfer) (&s390x->guest_v5.w64[1], buf, dir, size, mod); break;
+ case 58: VG_(transfer) (&s390x->guest_v6.w64[1], buf, dir, size, mod); break;
+ case 59: VG_(transfer) (&s390x->guest_v7.w64[1], buf, dir, size, mod); break;
+ case 60: VG_(transfer) (&s390x->guest_v8.w64[1], buf, dir, size, mod); break;
+ case 61: VG_(transfer) (&s390x->guest_v9.w64[1], buf, dir, size, mod); break;
+ case 62: VG_(transfer) (&s390x->guest_v10.w64[1], buf, dir, size, mod); break;
+ case 63: VG_(transfer) (&s390x->guest_v11.w64[1], buf, dir, size, mod); break;
+ case 64: VG_(transfer) (&s390x->guest_v12.w64[1], buf, dir, size, mod); break;
+ case 65: VG_(transfer) (&s390x->guest_v13.w64[1], buf, dir, size, mod); break;
+ case 66: VG_(transfer) (&s390x->guest_v14.w64[1], buf, dir, size, mod); break;
+ case 67: VG_(transfer) (&s390x->guest_v15.w64[1], buf, dir, size, mod); break;
+ case 68: VG_(transfer) (&s390x->guest_v16, buf, dir, size, mod); break;
+ case 69: VG_(transfer) (&s390x->guest_v17, buf, dir, size, mod); break;
+ case 70: VG_(transfer) (&s390x->guest_v18, buf, dir, size, mod); break;
+ case 71: VG_(transfer) (&s390x->guest_v19, buf, dir, size, mod); break;
+ case 72: VG_(transfer) (&s390x->guest_v20, buf, dir, size, mod); break;
+ case 73: VG_(transfer) (&s390x->guest_v21, buf, dir, size, mod); break;
+ case 74: VG_(transfer) (&s390x->guest_v22, buf, dir, size, mod); break;
+ case 75: VG_(transfer) (&s390x->guest_v23, buf, dir, size, mod); break;
+ case 76: VG_(transfer) (&s390x->guest_v24, buf, dir, size, mod); break;
+ case 77: VG_(transfer) (&s390x->guest_v25, buf, dir, size, mod); break;
+ case 78: VG_(transfer) (&s390x->guest_v26, buf, dir, size, mod); break;
+ case 79: VG_(transfer) (&s390x->guest_v27, buf, dir, size, mod); break;
+ case 80: VG_(transfer) (&s390x->guest_v28, buf, dir, size, mod); break;
+ case 81: VG_(transfer) (&s390x->guest_v29, buf, dir, size, mod); break;
+ case 82: VG_(transfer) (&s390x->guest_v30, buf, dir, size, mod); break;
+ case 83: VG_(transfer) (&s390x->guest_v31, buf, dir, size, mod); break;
default: vg_assert(0);
}
}
static
+Bool have_vx (void)
+{
+ VexArch va;
+ VexArchInfo vai;
+ VG_(machine_get_VexArchInfo) (&va, &vai);
+ return (vai.hwcaps & VEX_HWCAPS_S390X_VX) != 0;
+}
+
+static
const char* target_xml (Bool shadow_mode)
{
if (shadow_mode) {
- return "s390x-generic-valgrind.xml";
+ if (have_vx())
+ return "s390x-vx-linux-valgrind.xml";
+ else
+ return "s390x-generic-valgrind.xml";
} else {
- return "s390x-generic.xml";
- }
+ if (have_vx())
+ return "s390x-vx-linux.xml";
+ else
+ return "s390x-generic.xml";
+ }
}
static CORE_ADDR** target_get_dtv (ThreadState *tst)
@@ -206,7 +286,7 @@ static CORE_ADDR** target_get_dtv (Threa
}
static struct valgrind_target_ops low_target = {
- num_regs,
+ -1, // Override at init time.
regs,
17, //sp = r15, which is register offset 17 in regs
transfer_register,
@@ -220,6 +300,11 @@ static struct valgrind_target_ops low_ta
void s390x_init_architecture (struct valgrind_target_ops *target)
{
*target = low_target;
+ if (have_vx())
+ num_regs = num_regs_all;
+ else
+ num_regs = num_regs_all - 32; // Remove all VX registers.
+ target->num_regs = num_regs;
set_register_cache (regs, num_regs);
gdbserver_expedite_regs = expedite_regs;
}

42
0001-Bug-399444-s390x-Drop-unnecessary-check-in-s390_irge.patch
View File

@ -1,42 +0,0 @@
From ca2f73592e8e74a5328df0a65e0831bc1fc6dd28 Mon Sep 17 00:00:00 2001
From: Andreas Arnez <arnez@linux.ibm.com>
Date: Tue, 9 Oct 2018 11:22:27 +0200
Subject: [PATCH] Bug 399444 s390x: Drop unnecessary check in s390_irgen_VSLDB
In s390_irgen_VSLDB there was special handling for the case that the
immediate operand i4 has the value 16, which would mean that the result v1
were a full copy of the third operand v3. However, this is impossible
because i4 can only assume values from 0 to 15; thus the special handling
can be removed.
---
VEX/priv/guest_s390_toIR.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index c594ad51b..60b608138 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -17400,16 +17400,11 @@ s390_irgen_VSLDB(UChar v1, UChar v2, UChar v3, UChar i4)
{
UChar imm = i4 & 0b00001111;
- if (imm == 0)
- {
+ if (imm == 0) {
+ /* Just copy v2. */
put_vr_qw(v1, get_vr_qw(v2));
- }
- else if (imm == 16)
- {
- put_vr_qw(v1, get_vr_qw(v3));
- }
- else
- {
+ } else {
+ /* Concatenate v2's tail with v3's head. */
put_vr_qw(v1,
binop(Iop_OrV128,
binop(Iop_ShlV128, get_vr_qw(v2), mkU8(imm * 8)),
--
2.20.1

87
0001-Bug-400490-s390x-Fix-register-allocation-for-VRs-vs-.patch
View File

@ -1,87 +0,0 @@
From 71002d8a5111d02ce8049c55017a8d948c820e35 Mon Sep 17 00:00:00 2001
From: Andreas Arnez <arnez@linux.ibm.com>
Date: Thu, 25 Oct 2018 13:47:12 +0200
Subject: [PATCH] Bug 400490 s390x: Fix register allocation for VRs vs FPRs
On s390x, if vector registers are available, they are fed to the register
allocator as if they were separate from the floating-point registers. But
in fact the FPRs are embedded in the VRs. So for instance, if both f3 and
v3 are allocated and used at the same time, corruption will result.
This is fixed by offering only the non-overlapping VRs, v16 to v31, to the
register allocator instead.
---
NEWS | 1 +
VEX/priv/host_s390_defs.c | 17 +++++++----------
2 files changed, 8 insertions(+), 10 deletions(-)
Index: valgrind-3.14.0/VEX/priv/host_s390_defs.c
===================================================================
--- valgrind-3.14.0.orig/VEX/priv/host_s390_defs.c
+++ valgrind-3.14.0/VEX/priv/host_s390_defs.c
@@ -59,7 +59,6 @@ static UInt s390_tchain_load64_len(void)
/* A mapping from register number to register index */
static Int gpr_index[16]; // GPR regno -> register index
-static Int fpr_index[16]; // FPR regno -> register index
static Int vr_index[32]; // VR regno -> register index
HReg
@@ -73,7 +72,7 @@ s390_hreg_gpr(UInt regno)
HReg
s390_hreg_fpr(UInt regno)
{
- Int ix = fpr_index[regno];
+ Int ix = vr_index[regno];
vassert(ix >= 0);
return mkHReg(/*virtual*/False, HRcFlt64, regno, ix);
}
@@ -463,11 +462,9 @@ getRRegUniverse_S390(void)
RRegUniverse__init(ru);
- /* Assign invalid values to the gpr/fpr/vr_index */
+ /* Assign invalid values to the gpr/vr_index */
for (UInt i = 0; i < sizeof gpr_index / sizeof gpr_index[0]; ++i)
gpr_index[i] = -1;
- for (UInt i = 0; i < sizeof fpr_index / sizeof fpr_index[0]; ++i)
- fpr_index[i] = -1;
for (UInt i = 0; i < sizeof vr_index / sizeof vr_index[0]; ++i)
vr_index[i] = -1;
@@ -494,17 +491,17 @@ getRRegUniverse_S390(void)
ru->allocable_start[HRcFlt64] = ru->size;
for (UInt regno = 8; regno <= 15; ++regno) {
- fpr_index[regno] = ru->size;
+ vr_index[regno] = ru->size;
ru->regs[ru->size++] = s390_hreg_fpr(regno);
}
for (UInt regno = 0; regno <= 7; ++regno) {
- fpr_index[regno] = ru->size;
+ vr_index[regno] = ru->size;
ru->regs[ru->size++] = s390_hreg_fpr(regno);
}
ru->allocable_end[HRcFlt64] = ru->size - 1;
ru->allocable_start[HRcVec128] = ru->size;
- for (UInt regno = 0; regno <= 31; ++regno) {
+ for (UInt regno = 16; regno <= 31; ++regno) {
vr_index[regno] = ru->size;
ru->regs[ru->size++] = s390_hreg_vr(regno);
}
@@ -527,12 +524,12 @@ getRRegUniverse_S390(void)
/* Sanity checking */
for (UInt i = 0; i < sizeof gpr_index / sizeof gpr_index[0]; ++i)
vassert(gpr_index[i] >= 0);
- for (UInt i = 0; i < sizeof fpr_index / sizeof fpr_index[0]; ++i)
- vassert(fpr_index[i] >= 0);
for (UInt i = 0; i < sizeof vr_index / sizeof vr_index[0]; ++i)
vassert(vr_index[i] >= 0);
initialised = True;
+
+ RRegUniverse__check_is_sane(ru);
return ru;
}

45
0001-Bug-400491-s390x-Sign-extend-immediate-operand-of-LO.patch
View File

@ -1,45 +0,0 @@
From 9545e9f96beda6e9f2205bdb3c3e96edaf8d9e2b Mon Sep 17 00:00:00 2001
From: Andreas Arnez <arnez@linux.ibm.com>
Date: Tue, 30 Oct 2018 17:06:38 +0100
Subject: [PATCH] Bug 400491 s390x: Sign-extend immediate operand of LOCHI and
friends
The VEX implementation of each of the z/Architecture instructions LOCHI,
LOCHHI, and LOCGHI treats the immediate 16-bit operand as an unsigned
integer instead of a signed integer. This is fixed.
---
NEWS | 1 +
VEX/priv/guest_s390_toIR.c | 6 +++---
2 files changed, 4 insertions(+), 3 deletions(-)
Index: valgrind-3.14.0/VEX/priv/guest_s390_toIR.c
===================================================================
--- valgrind-3.14.0.orig/VEX/priv/guest_s390_toIR.c
+++ valgrind-3.14.0/VEX/priv/guest_s390_toIR.c
@@ -16307,7 +16307,7 @@ static const HChar *
s390_irgen_LOCHHI(UChar r1, UChar m3, UShort i2, UChar unused)
{
next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
- put_gpr_w0(r1, mkU32(i2));
+ put_gpr_w0(r1, mkU32((UInt)(Int)(Short)i2));
return "lochhi";
}
@@ -16316,7 +16316,7 @@ static const HChar *
s390_irgen_LOCHI(UChar r1, UChar m3, UShort i2, UChar unused)
{
next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
- put_gpr_w1(r1, mkU32(i2));
+ put_gpr_w1(r1, mkU32((UInt)(Int)(Short)i2));
return "lochi";
}
@@ -16325,7 +16325,7 @@ static const HChar *
s390_irgen_LOCGHI(UChar r1, UChar m3, UShort i2, UChar unused)
{
next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
- put_gpr_dw0(r1, mkU64(i2));
+ put_gpr_dw0(r1, mkU64((UInt)(Int)(Short)i2));
return "locghi";
}

273
0001-Bug-402519-POWER-3.0-addex-instruction-incorrectly-i.patch
View File

@ -1,273 +0,0 @@
From 35f3014237dc198356438b167725c6bec8b5bcaf Mon Sep 17 00:00:00 2001
From: Mark Wielaard <mark@klomp.org>
Date: Mon, 31 Dec 2018 22:26:31 +0100
Subject: [PATCH] Bug 402519 - POWER 3.0 addex instruction incorrectly
implemented
References: bsc#1121025
Patch-mainline: 3.15
Git-commit: 2c1f016e634bf79faf45e81c14c955c711bc202f
addex uses OV as carry in and carry out. For all other instructions
OV is the signed overflow flag. And instructions like adde use CA
as carry.
Replace set_XER_OV_OV32 with set_XER_OV_OV32_ADDEX, which will
call calculate_XER_CA_64 and calculate_XER_CA_32, but with OV
as input, and sets OV and OV32.
Enable test_addex in none/tests/ppc64/test_isa_3_0.c and update
the expected output. test_addex would fail to match the expected
output before this patch.
Acked-by: Michal Suchanek <msuchanek@suse.de>
---
NEWS | 1 +
VEX/priv/guest_ppc_toIR.c | 52 ++++++++++++-------
none/tests/ppc64/test_isa_3_0.c | 3 +-
.../ppc64/test_isa_3_0_other.stdout.exp-LE | 36 ++++++++-----
4 files changed, 58 insertions(+), 34 deletions(-)
diff --git a/NEWS b/NEWS
index 91e572e8d031..49df52158fa9 100644
--- a/NEWS
+++ b/NEWS
@@ -174,6 +174,7 @@ where XXXXXX is the bug number as listed below.
397424 glibc 2.27 and gdb_server tests
398028 Assertion `cfsi_fits` failing in simple C program
398066 s390x: cgijl dep1, 0 reports false unitialised values warning
+402519 POWER 3.0 addex instruction incorrectly implemented
n-i-bz Fix missing workq_ops operations (macOS)
n-i-bz fix bug in strspn replacement
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index cb1cae176af3..b6f4a6cde30f 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -2622,21 +2622,6 @@ static void copy_OV_to_OV32( void ) {
putXER_OV32( getXER_OV() );
}
-static void set_XER_OV_OV32 ( IRType ty, UInt op, IRExpr* res,
- IRExpr* argL, IRExpr* argR )
-{
- if (ty == Ity_I32) {
- set_XER_OV_OV32_32( op, res, argL, argR );
- } else {
- IRExpr* xer_ov_32;
- set_XER_OV_64( op, res, argL, argR );
- xer_ov_32 = calculate_XER_OV_32( op, unop(Iop_64to32, res),
- unop(Iop_64to32, argL),
- unop(Iop_64to32, argR));
- putXER_OV32( unop(Iop_32to8, xer_ov_32) );
- }
-}
-
static void set_XER_OV_OV32_SO ( IRType ty, UInt op, IRExpr* res,
IRExpr* argL, IRExpr* argR )
{
@@ -2982,6 +2967,33 @@ static void set_XER_CA_CA32 ( IRType ty, UInt op, IRExpr* res,
}
}
+/* Used only by addex instruction, which uses and sets OV as carry. */
+static void set_XER_OV_OV32_ADDEX ( IRType ty, IRExpr* res,
+ IRExpr* argL, IRExpr* argR,
+ IRExpr* old_ov )
+{
+ if (ty == Ity_I32) {
+ IRTemp xer_ov = newTemp(Ity_I32);
+ assign ( xer_ov, unop(Iop_32to8,
+ calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
+ res, argL, argR, old_ov ) ) );
+ putXER_OV( mkexpr (xer_ov) );
+ putXER_OV32( mkexpr (xer_ov) );
+ } else {
+ IRExpr *xer_ov;
+ IRExpr* xer_ov_32;
+ xer_ov = calculate_XER_CA_64( PPCG_FLAG_OP_ADDE,
+ res, argL, argR, old_ov );
+ putXER_OV( unop(Iop_32to8, xer_ov) );
+ xer_ov_32 = calculate_XER_CA_32( PPCG_FLAG_OP_ADDE,
+ unop(Iop_64to32, res),
+ unop(Iop_64to32, argL),
+ unop(Iop_64to32, argR),
+ unop(Iop_64to32, old_ov) );
+ putXER_OV32( unop(Iop_32to8, xer_ov_32) );
+ }
+}
+
/*------------------------------------------------------------*/
@@ -5071,16 +5083,18 @@ static Bool dis_int_arith ( UInt theInstr )
}
case 0xAA: {// addex (Add Extended alternate carry bit Z23-form)
+ IRTemp old_xer_ov = newTemp(ty);
DIP("addex r%u,r%u,r%u,%d\n", rD_addr, rA_addr, rB_addr, (Int)flag_OE);
+ assign( old_xer_ov, mkWidenFrom32(ty, getXER_OV_32(), False) );
assign( rD, binop( mkSzOp(ty, Iop_Add8), mkexpr(rA),
binop( mkSzOp(ty, Iop_Add8), mkexpr(rB),
- mkWidenFrom8( ty, getXER_OV(), False ) ) ) );
+ mkexpr(old_xer_ov) ) ) );
/* CY bit is same as OE bit */
if (flag_OE == 0) {
- /* Exception, do not set SO bit */
- set_XER_OV_OV32( ty, PPCG_FLAG_OP_ADDE,
- mkexpr(rD), mkexpr(rA), mkexpr(rB) );
+ /* Exception, do not set SO bit and set OV from carry. */
+ set_XER_OV_OV32_ADDEX( ty, mkexpr(rD), mkexpr(rA), mkexpr(rB),
+ mkexpr(old_xer_ov) );
} else {
/* CY=1, 2 and 3 (AKA flag_OE) are reserved */
vex_printf("addex instruction, CY = %d is reserved.\n", flag_OE);
diff --git a/none/tests/ppc64/test_isa_3_0.c b/none/tests/ppc64/test_isa_3_0.c
index 2d13505767f9..1c2cda361d04 100644
--- a/none/tests/ppc64/test_isa_3_0.c
+++ b/none/tests/ppc64/test_isa_3_0.c
@@ -286,7 +286,7 @@ static test_list_t testgroup_ia_ops_two[] = {
{ &test_moduw, "moduw" },
{ &test_modsd, "modsd" },
{ &test_modud, "modud" },
- //{ &test_addex, "addex" },
+ { &test_addex, "addex" },
{ NULL , NULL },
};
@@ -2741,7 +2741,6 @@ static void testfunction_gpr_vector_logical_one (const char* instruction_name,
* rt, xa
*/
int i;
- int t;
volatile HWord_t res;
VERBOSE_FUNCTION_CALLOUT
diff --git a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
index 152ff284b133..cc0e88e9a304 100644
--- a/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
+++ b/none/tests/ppc64/test_isa_3_0_other.stdout.exp-LE
@@ -40,7 +40,17 @@ modud ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000)
modud ffffffffffffffff, 0000001cbe991def => 000000043eb0c0b2 (00000000)
modud ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
-All done. Tested 4 different instructions
+addex 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
+addex 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000)
+addex 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000)
+addex 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000)
+addex 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000) OV32
+addex 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000) OV OV32
+addex ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000) OV OV32
+addex ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000) OV OV32
+addex ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000) OV OV32
+
+All done. Tested 5 different instructions
ppc one argument plus shift:
Test instruction group [ppc one argument plus shift]
extswsli aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff
@@ -85,7 +95,7 @@ extswsli. aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => aaaaaaaaaaaaaa
extswsli. 5152535455565758 5152535455565758 0 ffaa5599113377cc => 5152535455565758 5152535455565758 0 ffaa5599113377cc
extswsli. 0000000000000000 0000000000000000 0 ffaa5599113377cc => 0000000000000000 0000000000000000 0 ffaa5599113377cc
-All done. Tested 6 different instructions
+All done. Tested 7 different instructions
ppc three parameter ops:
Test instruction group [ppc three parameter ops]
maddhd 0000000000000000, 0000000000000000, 0000000000000000 => 0000000000000000 (00000000)
@@ -172,7 +182,7 @@ maddld ffffffffffffffff, ffffffffffffffff, 0000000000000000 => 000000000000000
maddld ffffffffffffffff, ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000)
maddld ffffffffffffffff, ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000)
-All done. Tested 9 different instructions
+All done. Tested 10 different instructions
ppc count zeros:
Test instruction group [ppc count zeros]
cnttzw 0000000000000000 => 0000000000000020
@@ -197,7 +207,7 @@ cnttzd. 0000001cbe991def => 0000000000000000 Expected cr0 to be zero, it is (200
cnttzd. ffffffffffffffff => 0000000000000000 Expected cr0 to be zero, it is (20000000)
-All done. Tested 13 different instructions
+All done. Tested 14 different instructions
ppc set boolean:
Test instruction group [ppc set boolean]
setb cr_field:0 cr_value::00000000 => 0000000000000000
@@ -265,7 +275,7 @@ setb cr_field:7 cr_value::00000005 => 0000000000000001
setb cr_field:7 cr_value::00000006 => 0000000000000001
setb cr_field:7 cr_value::00000007 => 0000000000000001
-All done. Tested 14 different instructions
+All done. Tested 15 different instructions
ppc char compare:
Test instruction group [ppc char compare]
cmprb l=0 0x61 (a) (cmpeq:0x5b427b625a417a61) (cmprb:src22(a-z) src21(A-Z)) => in range/found
@@ -1711,7 +1721,7 @@ cmpeqb 0x5d (]) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
cmpeqb 0x60 (`) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
cmpeqb 0x5f (_) (cmpeq:0x4642666245416561) (cmprb:src22(a-e) src21(A-E)) =>
-All done. Tested 17 different instructions
+All done. Tested 18 different instructions
ppc vector scalar move to/from:
Test instruction group [ppc vector scalar move to/from]
mfvsrld aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffffffffffffffff => aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa ffffffffffffffff
@@ -1777,7 +1787,7 @@ mtvsrws aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa 0 ffaa5599113377cc => 113377cc113377cc
mtvsrws 5152535455565758 5152535455565758 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
mtvsrws 0000000000000000 0000000000000000 0 ffaa5599113377cc => 113377cc113377cc 113377cc113377cc 0 ffaa5599113377cc
-All done. Tested 20 different instructions
+All done. Tested 21 different instructions
ppc dfp significance:
Test instruction group [ppc dfp significance]
dtstsfi significance(0x00) +Finite 0 * 10 ^ -12 (GT) (4)
@@ -1862,7 +1872,7 @@ dtstsfiq significance(0x20) -inf (GT) (4)
dtstsfiq significance(0x30) -inf (GT) (4)
dtstsfiq significance(0x3f) -inf (GT) (4)
-All done. Tested 22 different instructions
+All done. Tested 23 different instructions
ppc bcd misc:
Test instruction group [ppc bcd misc]
bcdadd. p0 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000000000000c (+|0) => (EQ) (2) xt:0000000000000000 000000000000000c(+|0)
@@ -33338,12 +33348,12 @@ bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:9999999999999999 99999
bcdcfsq. p1 xa:0000000000000000 000000000000000c (+|0) xb:0000000000000000 000000001234567d ( - ) => (GT) (4) xt:0000000000000000 000000305419901f(+|0)
-All done. Tested 51 different instructions
+All done. Tested 52 different instructions
ppc noop misc:
Test instruction group [ppc noop misc]
wait =>
-All done. Tested 52 different instructions
+All done. Tested 53 different instructions
ppc addpc_misc:
Test instruction group [ppc addpc_misc]
addpcis 0000000000000000 => 0000000000000000
@@ -33380,7 +33390,7 @@ subpcis 000000000000000d => 0000000000000000
subpcis 000000000000000e => 0000000000000000
subpcis 000000000000000f => 0000000000000000
-All done. Tested 54 different instructions
+All done. Tested 55 different instructions
ppc mffpscr:
Test instruction group [ppc mffpscr]
mffsce => 000000000.000000
@@ -33395,7 +33405,7 @@ mffs => 000000000.000000
fpscr: f14
local_fpscr:
-All done. Tested 57 different instructions
+All done. Tested 58 different instructions
ppc mffpscr:
Test instruction group [ppc mffpscr]
mffscdrni 0 => 0X0
@@ -33426,4 +33436,4 @@ mffscrn f15 0X1 => 0X200000000
mffscrn f15 0X2 => 0X200000000
fpscr: f14 local_fpscr: 30-DRN1 RN-bit62
-All done. Tested 61 different instructions
+All done. Tested 62 different instructions
--
2.19.2

46
0001-Bug-403552-s390x-Fix-vector-facility-bit-number.patch
View File

@ -1,46 +0,0 @@
From 467c7c4c9665c0f8b41a4416722a027ebc05df2b Mon Sep 17 00:00:00 2001
From: Andreas Arnez <arnez@linux.ibm.com>
Date: Mon, 21 Jan 2019 14:10:00 +0100
Subject: [PATCH] Bug 403552 s390x: Fix vector facility bit number
The wrong bit number was used when checking for the vector facility. This
can result in a fatal emulation error: "Encountered an instruction that
requires the vector facility. That facility is not available on this
host."
In many cases the wrong facility bit was usually set as well, hence
nothing bad happened. But when running Valgrind within a Qemu/KVM guest,
the wrong bit was not (always?) set and the emulation error occurred.
This fix simply corrects the vector facility bit number, changing it from
128 to 129.
---
NEWS | 1 +
VEX/pub/libvex_s390x_common.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
Index: valgrind-3.14.0/NEWS
===================================================================
--- valgrind-3.14.0.orig/NEWS
+++ valgrind-3.14.0/NEWS
@@ -175,6 +175,7 @@ where XXXXXX is the bug number as listed
398028 Assertion `cfsi_fits` failing in simple C program
398066 s390x: cgijl dep1, 0 reports false unitialised values warning
402519 POWER 3.0 addex instruction incorrectly implemented
+403552 s390x: wrong facility bit checked for vector facility
n-i-bz Fix missing workq_ops operations (macOS)
n-i-bz fix bug in strspn replacement
Index: valgrind-3.14.0/VEX/pub/libvex_s390x_common.h
===================================================================
--- valgrind-3.14.0.orig/VEX/pub/libvex_s390x_common.h
+++ valgrind-3.14.0/VEX/pub/libvex_s390x_common.h
@@ -103,7 +103,7 @@
#define S390_FAC_MSA5 57 // message-security-assist 5
#define S390_FAC_TREXE 73 // transactional execution
#define S390_FAC_MSA4 77 // message-security-assist 4
-#define S390_FAC_VX 128 // vector facility
+#define S390_FAC_VX 129 // vector facility
/*--------------------------------------------------------------*/

51
0001-s390x-more-fixes.patch
View File

@ -1,51 +0,0 @@
From d10cd86ee32bf76495f79c02df62fc242adbcbe3 Mon Sep 17 00:00:00 2001
From: Andreas Arnez <arnez@linux.vnet.ibm.com>
Date: Thu, 26 Jul 2018 16:35:24 +0200
Subject: [PATCH] s390x: More fixes for z13 support
This patch addresses the following:
* Fix the implementation of LOCGHI. Previously Valgrind performed 32-bit
sign extension instead of 64-bit sign extension on the immediate value.
* Advertise VXRS in HWCAP. If no VXRS are advertised, but the program
uses vector registers, this could cause problems with a glibc built with
"-march=z13".
---
VEX/priv/guest_s390_toIR.c | 2 +-
coregrind/m_initimg/initimg-linux.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
index 9c4d79b87..50a5a4177 100644
--- a/VEX/priv/guest_s390_toIR.c
+++ b/VEX/priv/guest_s390_toIR.c
@@ -16325,7 +16325,7 @@ static const HChar *
s390_irgen_LOCGHI(UChar r1, UChar m3, UShort i2, UChar unused)
{
next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0)));
- put_gpr_dw0(r1, mkU64((UInt)(Int)(Short)i2));
+ put_gpr_dw0(r1, mkU64((ULong)(Long)(Short)i2));
return "locghi";
}
diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
index 61cc458bc..8a7f0d024 100644
--- a/coregrind/m_initimg/initimg-linux.c
+++ b/coregrind/m_initimg/initimg-linux.c
@@ -699,9 +699,9 @@ Addr setup_client_stack( void* init_sp,
}
# elif defined(VGP_s390x_linux)
{
- /* Advertise hardware features "below" TE only. TE and VXRS
- (and anything above) are not supported by Valgrind. */
- auxv->u.a_val &= VKI_HWCAP_S390_TE - 1;
+ /* Advertise hardware features "below" TE and VXRS. TE itself
+ and anything above VXRS is not supported by Valgrind. */
+ auxv->u.a_val &= (VKI_HWCAP_S390_TE - 1) | VKI_HWCAP_S390_VXRS;
}
# elif defined(VGP_arm64_linux)
{
--
2.17.0

376
Implement-emulated-system-registers.-Fixes-392146.patch
View File

@ -1,376 +0,0 @@
From a940156fc32b0c49e847aec0e4076161241cfa15 Mon Sep 17 00:00:00 2001
From: Matthias Brugger <mbrugger@suse.com>
Date: Wed, 6 Jun 2018 15:23:07 +0200
Subject: [PATCH] Implement emulated system registers. Fixes #392146.
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
---
VEX/priv/guest_arm64_defs.h | 9 ++
VEX/priv/guest_arm64_helpers.c | 100 +++++++++++++++
VEX/priv/guest_arm64_toIR.c | 222 +++++++++++++++++++++++++++++++++
3 files changed, 331 insertions(+)
Index: valgrind-3.14.0/VEX/priv/guest_arm64_defs.h
===================================================================
--- valgrind-3.14.0.orig/VEX/priv/guest_arm64_defs.h
+++ valgrind-3.14.0/VEX/priv/guest_arm64_defs.h
@@ -126,6 +126,15 @@ extern ULong arm64g_dirtyhelper_MRS_CNTV
extern ULong arm64g_dirtyhelper_MRS_CNTFRQ_EL0 ( void );
+extern ULong arm64g_dirtyhelper_MRS_MIDR_EL1 ( void );
+
+extern ULong arm64g_dirtyhelper_MRS_ID_AA64PFR0_EL1 ( void );
+
+extern ULong arm64g_dirtyhelper_MRS_ID_AA64MMFR0_EL1 ( void );
+extern ULong arm64g_dirtyhelper_MRS_ID_AA64MMFR1_EL1 ( void );
+
+extern ULong arm64g_dirtyhelper_MRS_ID_AA64ISAR0_EL1 ( void );
+
extern void arm64g_dirtyhelper_PMULLQ ( /*OUT*/V128* res,
ULong arg1, ULong arg2 );
Index: valgrind-3.14.0/VEX/priv/guest_arm64_helpers.c
===================================================================
--- valgrind-3.14.0.orig/VEX/priv/guest_arm64_helpers.c
+++ valgrind-3.14.0/VEX/priv/guest_arm64_helpers.c
@@ -788,6 +788,106 @@ ULong arm64g_dirtyhelper_MRS_CNTFRQ_EL0
# endif
}
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-arm64 platforms, return 0. */
+ULong arm64g_dirtyhelper_MRS_MIDR_EL1 ( void )
+{
+# if defined(__aarch64__) && !defined(__arm__)
+ ULong w = 0x5555555555555555ULL; /* overwritten */
+ __asm__ __volatile__("mrs %0, midr_el1" : "=r"(w));
+ return w;
+# else
+ return 0ULL;
+# endif
+}
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-arm64 platforms, return 0. */
+ULong arm64g_dirtyhelper_MRS_ID_AA64PFR0_EL1 ( void )
+{
+# if defined(__aarch64__) && !defined(__arm__)
+ ULong w = 0x5555555555555555ULL; /* overwritten */
+ __asm__ __volatile__("mrs %0, id_aa64pfr0_el1" : "=r"(w));
+
+ /* If half-precision fp is present we fall back to normal
+ half precision implementation because of missing support in the emulation.
+ If no AdvSIMD and FP are implemented, we preserve the value */
+ w = (w >> 16);
+ w &= 0xff;
+ switch(w) {
+ case 0x11:
+ w = 0x0;
+ break;
+ case 0xff:
+ w = (0xFF<<16);
+ break;
+ default:
+ w = 0x0;
+ break;
+ }
+
+ return w;
+# else
+ return 0ULL;
+# endif
+}
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-arm64 platforms, return 0. */
+ULong arm64g_dirtyhelper_MRS_ID_AA64MMFR0_EL1 ( void )
+{
+# if defined(__aarch64__) && !defined(__arm__)
+ ULong w = 0x5555555555555555ULL; /* overwritten */
+ __asm__ __volatile__("mrs %0, id_aa64mmfr0_el1" : "=r"(w));
+ return w;
+# else
+ return 0ULL;
+# endif
+}
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-arm64 platforms, return 0. */
+ULong arm64g_dirtyhelper_MRS_ID_AA64MMFR1_EL1 ( void )
+{
+# if defined(__aarch64__) && !defined(__arm__)
+ ULong w = 0x5555555555555555ULL; /* overwritten */
+ __asm__ __volatile__("mrs %0, id_aa64mmfr1_el1" : "=r"(w));
+
+ /* Clear VH and HAFDBS bits */
+ w &= ~(0xF0F);
+ return w;
+# else
+ return 0ULL;
+# endif
+}
+
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-arm64 platforms, return 0. */
+ULong arm64g_dirtyhelper_MRS_ID_AA64ISAR0_EL1 ( void )
+{
+# if defined(__aarch64__) && !defined(__arm__)
+ ULong w = 0x5555555555555555ULL; /* overwritten */
+ __asm__ __volatile__("mrs %0, id_aa64isar0_el1" : "=r"(w));
+
+ /* Clear all but AES, SHA1 and SHA2 parts*/
+ w &= ~0xFFFF;
+ /* Degredate SHA2 from b0010 to b0001*/
+ if ( (w >> 12) & 0x2 ) {
+ w &= ~(0xF << 12);
+ w |= (0x1 << 12);
+ }
+
+ return w;
+# else
+ return 0ULL;
+# endif
+}
+
void arm64g_dirtyhelper_PMULLQ ( /*OUT*/V128* res, ULong arg1, ULong arg2 )
{
Index: valgrind-3.14.0/VEX/priv/guest_arm64_toIR.c
===================================================================
--- valgrind-3.14.0.orig/VEX/priv/guest_arm64_toIR.c
+++ valgrind-3.14.0/VEX/priv/guest_arm64_toIR.c
@@ -6891,6 +6891,228 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisR
}
/* ------------------ M{SR,RS} ------------------ */
+ /* ---- Case for MIDR_EL1 (RO) ----
+ Read the Main ID register from host.
+ 0xD53800 000 Rt MRS rT, midr_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380000 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ IRTemp val = newTemp(Ity_I64);
+ IRExpr** args = mkIRExprVec_0();
+ IRDirty* d = unsafeIRDirty_1_N (
+ val,
+ 0/*regparms*/,
+ "arm64g_dirtyhelper_MRS_MIDR_EL1",
+ &arm64g_dirtyhelper_MRS_MIDR_EL1,
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIReg64orZR(tt, mkexpr(val));
+ DIP("mrs %s, midr_el1\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for MPIDR_EL1 (RO) ----
+ Instead of returing a fake regiser, we use the same
+ value as does the kernel emulation.
+ 0xD53800 101 Rt MRS rT, mpidr_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53800A0 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64((1UL<<31)));
+ DIP("mrs %s, mpidr_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for REVDIR_EL1 (RO) ----
+ Instead of emulating the regiser, we just return the same
+ value as does the kernel emulation.
+ 0xD53800 110 Rt MRS rT, revdir_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53800C0 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg32orZR(tt, mkU32(0x0));
+ DIP("mrs %s, revdir_el1 (FAKED)\n", nameIReg32orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64PFR0_EL1 (RO) ----
+ Instead of returing a fake regiser, we use the same
+ value as does the kernel emulation. We set deprecate half
+ precission floating-point to normal floating-point support.
+ We set all other values to zero.
+ 0xD53804 000 Rt MRS rT, id_aa64pfr0_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380400 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ IRTemp val = newTemp(Ity_I64);
+ IRExpr** args = mkIRExprVec_0();
+ IRDirty* d = unsafeIRDirty_1_N (
+ val,
+ 0/*regparms*/,
+ "arm64g_dirtyhelper_MRS_ID_AA64PFR0_EL1",
+ &arm64g_dirtyhelper_MRS_ID_AA64PFR0_EL1,
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+
+ putIReg64orZR(tt, mkexpr(val));
+ return True;
+ }
+ /* ---- Case for ID_AA64PFR1_EL1 (RO) ----
+ We just return 0x0 here, as we don't support the opcodes of
+ new commands in the emulation environment.
+ 0xD53804 001 Rt MRS rT, id_aa64pfr1_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380420 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x0));
+ DIP("mrs %s, id_aa64pfr1_el1 (FAKED)\n", nameIReg32orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64ZFR0_EL1 (RO) ----
+ We just return 0x0 here, as we don't support the opcodes of
+ new commands in the emulation environment.
+ 0xD53804 010 Rt MRS rT, id_aa64zfr0_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380440 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x0));
+ DIP("mrs %s, id_aa64zfr0_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64DFR0_EL1 (RO) ----
+ Just return the value indicating the implementation of the
+ ARMv8 debug architecture without any extensions.
+ 0xD53805 000 Rt MRS rT, id_aa64dfr0_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380500 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x6));
+ DIP("mrs %s, id_aa64dfr0_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64DFR1_EL1 (RO) ----
+ We just return 0x0 here, as we don't support the opcodes of
+ new commands in the emulation environment.
+ 0xD53805 001 Rt MRS rT, id_aa64dfr1_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380520 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x0));
+ DIP("mrs %s, id_aa64dfr1_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64AFR0_EL1 (RO) ----
+ We just return 0x0 here, as we don't support the opcodes of
+ new commands in the emulation environment.
+ 0xD53805 100 Rt MRS rT, id_aa64afr0_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380580 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x0));
+ DIP("mrs %s, id_aa64afr0_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64AFR1_EL1 (RO) ----
+ We just return 0x0 here, as we don't support the opcodes of
+ new commands in the emulation environment.
+ 0xD53805 101 Rt MRS rT, id_aa64afr1_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD53805A0 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x0));
+ DIP("mrs %s, id_aa64afr1_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64ISAR0_EL1 (RO) ----
+ We only take care of SHA2, SHA1 and AES bits, as all the other
+ commands are not part of the emulation environment.
+ We degredate SHA2 from 0x2 to 0x1 as we don't support the commands.
+ 0xD53806 000 Rt MRS rT, id_aa64isar0_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380600 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ IRTemp val = newTemp(Ity_I64);
+ IRExpr** args = mkIRExprVec_0();
+ IRDirty* d = unsafeIRDirty_1_N (
+ val,
+ 0/*regparms*/,
+ "arm64g_dirtyhelper_MRS_ID_AA64ISAR0_EL1",
+ &arm64g_dirtyhelper_MRS_ID_AA64ISAR0_EL1,
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIReg64orZR(tt, mkexpr(val));
+ DIP("mrs %s, id_aa64isar0_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64ISAR1_EL1 (RO) ----
+ We just return 0x0 here, as we don't support the opcodes of
+ new commands in the emulation environment.
+ 0xD53806 001 Rt MRS rT, id_aa64isar1_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380620 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x0));
+ DIP("mrs %s, id_aa64isar1_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64MMFR0_EL1 (RO) ----
+ Instead of returing a fake regiser, we use the same
+ value as does the kernel emulation.
+ 0xD53807 000 Rt MRS rT, id_aa64mmfr0_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380700 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ IRTemp val = newTemp(Ity_I64);
+ IRExpr** args = mkIRExprVec_0();
+ IRDirty* d = unsafeIRDirty_1_N (
+ val,
+ 0/*regparms*/,
+ "arm64g_dirtyhelper_MRS_ID_AA64MMFR0_EL1",
+ &arm64g_dirtyhelper_MRS_ID_AA64MMFR0_EL1,
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIReg64orZR(tt, mkexpr(val));
+ DIP("mrs %s, id_aa64mmfr0_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64MMFR1_EL1 (RO) ----
+ Instead of returing a fake regiser, we use the same
+ value as does the kernel emulation. Set VHE and HAFDBS
+ to not implemented.
+ 0xD53807 001 Rt MRS rT, id_aa64mmfr1_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380720 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ IRTemp val = newTemp(Ity_I64);
+ IRExpr** args = mkIRExprVec_0();
+ IRDirty* d = unsafeIRDirty_1_N (
+ val,
+ 0/*regparms*/,
+ "arm64g_dirtyhelper_MRS_ID_AA64MMFR1_EL1",
+ &arm64g_dirtyhelper_MRS_ID_AA64MMFR1_EL1,
+ args
+ );
+ /* execute the dirty call, dumping the result in val. */
+ stmt( IRStmt_Dirty(d) );
+ putIReg64orZR(tt, mkexpr(val));
+ DIP("mrs %s, id_aa64mmfr1_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
+ /* ---- Case for ID_AA64MMFR2_EL1 (RO) ----
+ Return faked value of not implemented ARMv8.2 and ARMv8.3
+ 0xD53807 010 Rt MRS rT, id_aa64mmfr2_el1
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD5380740 /*MRS*/) {
+ UInt tt = INSN(4,0);
+ putIReg64orZR(tt, mkU64(0x0));
+ DIP("mrs %s, id_aa64mmfr2_el1 (FAKED)\n", nameIReg64orZR(tt));
+ return True;
+ }
/* ---- Cases for TPIDR_EL0 ----
0xD51BD0 010 Rt MSR tpidr_el0, rT
0xD53BD0 010 Rt MRS rT, tpidr_el0

3
valgrind-3.14.0.tar.bz2
View File

@ -1,3 +0,0 @@
version https://git-lfs.github.com/spec/v1
oid sha256:037c11bfefd477cc6e9ebe8f193bb237fe397f7ce791b4a4ce3fa1c6a520baa5
size 16602858

3
valgrind-3.15.0.tar.bz2 Normal file
View File

@ -0,0 +1,3 @@
version https://git-lfs.github.com/spec/v1
oid sha256:417c7a9da8f60dd05698b3a7bc6002e4ef996f14c13f0ff96679a16873e78ab1
size 20241437

77
valgrind.changes
View File

@ -1,3 +1,80 @@
-------------------------------------------------------------------
Wed May 8 15:36:12 UTC 2019 - Dirk Mueller <dmueller@suse.com>
- update to 3.15.0 (fate#327402):
3.15.0 is a feature release with many improvements and the usual collection of
bug fixes.
This release supports X86/Linux, AMD64/Linux, ARM32/Linux, ARM64/Linux,
PPC32/Linux, PPC64BE/Linux, PPC64LE/Linux, S390X/Linux, MIPS32/Linux,
MIPS64/Linux, ARM/Android, ARM64/Android, MIPS32/Android, X86/Android,
X86/Solaris, AMD64/Solaris and AMD64/MacOSX 10.12. There is also preliminary
support for X86/macOS 10.13 and AMD64/macOS 10.13.
* ==================== CORE CHANGES ===================
* The XTree Massif output format now makes use of the information obtained
when specifying --read-inline-info=yes.
* amd64 (x86_64): the RDRAND and F16C insn set extensions are now supported.
* ==================== TOOL CHANGES ====================
* DHAT:
- DHAT been thoroughly overhauled, improved, and given a GUI. As a result,
it has been promoted from an experimental tool to a regular tool. Run it
with --tool=dhat instead of --tool=exp-dhat.
- DHAT now prints only minimal data when the program ends, instead writing
the bulk of the profiling data to a file. As a result, the --show-top-n
and --sort-by options have been removed.
- Profile results can be viewed with the new viewer, dh_view.html. When
a run ends, a short message is printed, explaining how to view the result.
- See the documentation for more details.
* Cachegrind:
- cg_annotate has a new option, --show-percs, which prints percentages next
to all event counts.
* Callgrind:
- callgrind_annotate has a new option, --show-percs, which prints percentages
next to all event counts.
- callgrind_annotate now inserts commas in call counts, and
sort the caller/callee lists in the call tree.
* Massif:
- The default value for --read-inline-info is now "yes" on
Linux/Android/Solaris. It is still "no" on other OS.
* Memcheck:
- The option --xtree-leak=yes (to output leak result in xtree format)
automatically activates the option --show-leak-kinds=all, as xtree
visualisation tools such as kcachegrind can in any case select what kind
of leak to visualise.
- There has been further work to avoid false positives. In particular,
integer equality on partially defined inputs (C == and !=) is now handled
better.
- remove 0001-Bug-385411-s390x-Add-z13-vector-floating-point-suppo.patch
0001-Bug-385411-s390x-Tests-and-internals-for-z13-vector-.patch
0001-Bug-397187-s390x-Add-vector-register-support-for-vgd.patch
0001-Bug-399444-s390x-Drop-unnecessary-check-in-s390_irge.patch
0001-Bug-400490-s390x-Fix-register-allocation-for-VRs-vs-.patch
0001-Bug-400491-s390x-Sign-extend-immediate-operand-of-LO.patch
0001-Bug-402519-POWER-3.0-addex-instruction-incorrectly-i.patch
0001-Bug-403552-s390x-Fix-vector-facility-bit-number.patch
0001-s390x-more-fixes.patch
Implement-emulated-system-registers.-Fixes-392146.patch (all upstream)
-------------------------------------------------------------------
Wed Apr 24 17:43:06 UTC 2019 - Martin Liška <mliska@suse.cz>

24
valgrind.spec
View File

@ -22,7 +22,7 @@
%define building_docs 1
Name: valgrind
Version: 3.14.0
Version: 3.15.0
Release: 0
Summary: Memory Management Debugger
License: GPL-2.0-or-later
@ -34,16 +34,6 @@ Source0: ftp://sourceware.org/pub/valgrind/valgrind-%{version}.tar.bz2
Patch0: valgrind.xen.patch
Patch1: jit-register-unregister.diff
Patch2: armv6-support.diff
Patch4: Implement-emulated-system-registers.-Fixes-392146.patch
Patch5: 0001-Bug-400490-s390x-Fix-register-allocation-for-VRs-vs-.patch
Patch6: 0001-Bug-400491-s390x-Sign-extend-immediate-operand-of-LO.patch
Patch7: 0001-Bug-397187-s390x-Add-vector-register-support-for-vgd.patch
Patch8: 0001-s390x-more-fixes.patch
Patch9: 0001-Bug-402519-POWER-3.0-addex-instruction-incorrectly-i.patch
Patch10: 0001-Bug-399444-s390x-Drop-unnecessary-check-in-s390_irge.patch
Patch11: 0001-Bug-385411-s390x-Add-z13-vector-floating-point-suppo.patch
Patch12: 0001-Bug-403552-s390x-Fix-vector-facility-bit-number.patch
Patch13: 0001-Bug-385411-s390x-Tests-and-internals-for-z13-vector-.patch
BuildRequires: automake
BuildRequires: docbook-xsl-stylesheets
BuildRequires: docbook_4
@ -151,16 +141,6 @@ but it has been successfully used to optimize several KDE applications.
# needs porting to 3.11
##%patch1
%patch2
%patch4 -p1
%patch5 -p1
%patch6 -p1
%patch7 -p1
%patch8 -p1
%patch9 -p1
%patch10 -p1
%patch11 -p1
%patch12 -p1
%patch13 -p1
%build
%define _lto_cflags %{nil}
@ -256,6 +236,8 @@ VALGRIND_LIB=$PWD/.in_place VALGRIND_LIB_INNER=$PWD/.in_place ./coregrind/valgri
%ifarch %arm
%{_libdir}/valgrind/*-arm-linux
%endif
%dir /usr/lib/valgrind
/usr/lib/valgrind/dh_view*
%{_libdir}/valgrind/*-linux.so
%{_libdir}/valgrind/*.supp
%{_libdir}/valgrind/64bit-core.xml