29 lines
1.0 KiB
Diff
29 lines
1.0 KiB
Diff
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References: FATE#309893
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# HG changeset patch
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# User Mark Langsdorf <mark.langsdorf@amd.com>
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# Date 1308051989 -3600
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# Node ID 450f1d198e1e299b69489d513f591f0301cc5166
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# Parent 864a3dd1d9b4664f1ece44c9eaf390969253b7a8
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x86/amd: Eliminate cache flushing when entering C3 on select AMD processors
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AMD Fam15h processors have a shared cache. It does not need
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to be be flushed when entering C3 and doing so causes reduces
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performance. Modify acpi_processor_power_init_bm_check to
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prevent these processors from flushing when entering C3.
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Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
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--- a/xen/arch/x86/acpi/cpu_idle.c
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+++ b/xen/arch/x86/acpi/cpu_idle.c
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@@ -680,7 +680,8 @@ static void acpi_processor_power_init_bm
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flags->bm_check = 0;
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if ( num_online_cpus() == 1 )
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flags->bm_check = 1;
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- else if ( c->x86_vendor == X86_VENDOR_INTEL )
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+ else if ( (c->x86_vendor == X86_VENDOR_INTEL) ||
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+ ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) )
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{
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/*
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* Today all MP CPUs that support C3 share cache.
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