1b78387def
- fate#309901: Add Xen support for SVM TSC scaling in AMD family 15h - fate#311951: Ivy Bridge: XEN support for Supervisor Mode Execution Protection (SMEP) 23437-amd-fam15-TSC-scaling.patch 23462-libxc-cpu-feature.patch 23481-x86-SMEP.patch 23504-x86-SMEP-hvm.patch 23505-x86-cpu-add-arg-check.patch 23508-vmx-proc-based-ctls-probe.patch 23510-hvm-cpuid-DRNG.patch 23511-amd-fam15-no-flush-for-C3.patch 23516-cpuid-ERMS.patch 23538-hvm-pio-emul-no-host-crash.patch 23539-hvm-cpuid-FSGSBASE.patch 23543-x86_64-maddr_to_virt-assertion.patch 23546-fucomip.patch - Fix libxc reentrancy issues 23383-libxc-rm-static-vars.patch OBS-URL: https://build.opensuse.org/package/show/Virtualization/xen?expand=0&rev=128
29 lines
1.0 KiB
Diff
29 lines
1.0 KiB
Diff
References: FATE#309893
|
|
|
|
# HG changeset patch
|
|
# User Mark Langsdorf <mark.langsdorf@amd.com>
|
|
# Date 1308051989 -3600
|
|
# Node ID 450f1d198e1e299b69489d513f591f0301cc5166
|
|
# Parent 864a3dd1d9b4664f1ece44c9eaf390969253b7a8
|
|
x86/amd: Eliminate cache flushing when entering C3 on select AMD processors
|
|
|
|
AMD Fam15h processors have a shared cache. It does not need
|
|
to be be flushed when entering C3 and doing so causes reduces
|
|
performance. Modify acpi_processor_power_init_bm_check to
|
|
prevent these processors from flushing when entering C3.
|
|
|
|
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
|
|
|
|
--- a/xen/arch/x86/acpi/cpu_idle.c
|
|
+++ b/xen/arch/x86/acpi/cpu_idle.c
|
|
@@ -680,7 +680,8 @@ static void acpi_processor_power_init_bm
|
|
flags->bm_check = 0;
|
|
if ( num_online_cpus() == 1 )
|
|
flags->bm_check = 1;
|
|
- else if ( c->x86_vendor == X86_VENDOR_INTEL )
|
|
+ else if ( (c->x86_vendor == X86_VENDOR_INTEL) ||
|
|
+ ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 0x15)) )
|
|
{
|
|
/*
|
|
* Today all MP CPUs that support C3 share cache.
|