Accepting request 1325490 from devel:libraries:c_c++

- add 0001-Revert-Extend-1172-approach-to-arm-store-version.patch
  to fix test failures on aarch64 (gh#xtensor-stack/xsimd#1232)

- Deduplicate files in %install using %fdupes macro
- Make the -devel and the -doc packages noarch

OBS-URL: https://build.opensuse.org/request/show/1325490
OBS-URL: https://build.opensuse.org/package/show/openSUSE:Factory/xsimd?expand=0&rev=14

0001-Fix-xsimd-available_architectures-.has-for-sve-and-r.patch

@@ -1,87 +0,0 @@
-From 4f91d4a44eb9476572cf49a96cbe658eb871f47c Mon Sep 17 00:00:00 2001
-From: Dmitry Kazakov <dimula73@gmail.com>
-Date: Fri, 14 Jun 2024 10:19:55 +0200
-Subject: [PATCH 1/2] Fix xsimd::available_architectures().has() for sve and
- rvv archs
-
-Ideally the patch CPU detection code should also check if the length
-of SVE and RVV is actually supported by the current CPU implementation
-(i.e. ZCR_Elx.LEN register for SVE and something else for RVV), but
-I don't have such CPUs/emulators handy, so I cannot add such checks.
-
-Given that xsimd::available_architectures().has() is a new feature
-of XSIMD13 and the length check has never been present in XSIMD, this
-bug is not a regression at least.
-
-The patch also adds a unittest that reproduces the error the patch fixes
----
- include/xsimd/config/xsimd_cpuid.hpp | 12 ++++++++++--
- test/test_arch.cpp                   | 15 +++++++++++++++
- 2 files changed, 25 insertions(+), 2 deletions(-)
-
-diff --git a/include/xsimd/config/xsimd_cpuid.hpp b/include/xsimd/config/xsimd_cpuid.hpp
-index f22089b..30a9da2 100644
---- a/include/xsimd/config/xsimd_cpuid.hpp
-+++ b/include/xsimd/config/xsimd_cpuid.hpp
-@@ -42,6 +42,10 @@ namespace xsimd
- #define ARCH_FIELD_EX(arch, field_name) \
-     unsigned field_name;                \
-     XSIMD_INLINE bool has(::xsimd::arch) const { return this->field_name; }
-+
-+#define ARCH_FIELD_EX_REUSE(arch, field_name) \
-+    XSIMD_INLINE bool has(::xsimd::arch) const { return this->field_name; }
-+
- #define ARCH_FIELD(name) ARCH_FIELD_EX(name, name)
- 
-             ARCH_FIELD(sse2)
-@@ -72,8 +76,12 @@ namespace xsimd
-             ARCH_FIELD(neon)
-             ARCH_FIELD(neon64)
-             ARCH_FIELD_EX(i8mm<::xsimd::neon64>, i8mm_neon64)
--            ARCH_FIELD(sve)
--            ARCH_FIELD(rvv)
-+            ARCH_FIELD_EX(detail::sve<512>, sve)
-+            ARCH_FIELD_EX_REUSE(detail::sve<256>, sve)
-+            ARCH_FIELD_EX_REUSE(detail::sve<128>, sve)
-+            ARCH_FIELD_EX(detail::rvv<512>, rvv)
-+            ARCH_FIELD_EX_REUSE(detail::rvv<256>, rvv)
-+            ARCH_FIELD_EX_REUSE(detail::rvv<128>, rvv)
-             ARCH_FIELD(wasm)
- 
- #undef ARCH_FIELD
-diff --git a/test/test_arch.cpp b/test/test_arch.cpp
-index b420733..f1f50d5 100644
---- a/test/test_arch.cpp
-+++ b/test/test_arch.cpp
-@@ -38,6 +38,16 @@ struct check_supported
-     }
- };
- 
-+struct check_cpu_has_intruction_set
-+{
-+    template <class Arch>
-+    void operator()(Arch arch) const
-+    {
-+        static_assert(std::is_same<decltype(xsimd::available_architectures().has(arch)), bool>::value,
-+                      "cannot test instruction set availability on CPU");
-+    }
-+};
-+
- struct check_available
- {
-     template <class Arch>
-@@ -71,6 +81,11 @@ TEST_CASE("[multi arch support]")
-         xsimd::supported_architectures::for_each(check_supported {});
-     }
- 
-+    SUBCASE("xsimd::available_architectures::has")
-+    {
-+        xsimd::all_architectures::for_each(check_cpu_has_intruction_set {});
-+    }
-+
-     SUBCASE("xsimd::default_arch::name")
-     {
-         constexpr char const* name = xsimd::default_arch::name();
--- 
-2.45.2
-

0001-Revert-Extend-1172-approach-to-arm-store-version.patch

@@ -0,0 +1,83 @@
+From c489b1869aa1eb21d3dc7f361e30e9d0c1c823e9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Dirk=20M=C3=BCller?= <dirk@dmllr.de>
+Date: Mon, 5 Jan 2026 23:04:35 +0100
+Subject: [PATCH] Revert "Extend #1172 approach to arm - store version"
+
+This reverts commit eb17eaaa30129a65042bedf245658014ffd94232.
+---
+ include/xsimd/arch/xsimd_neon.hpp   | 37 -----------------------------
+ include/xsimd/arch/xsimd_neon64.hpp | 10 --------
+ 2 files changed, 47 deletions(-)
+
+diff --git a/include/xsimd/arch/xsimd_neon.hpp b/include/xsimd/arch/xsimd_neon.hpp
+index 55b3b8d..7e3c7bb 100644
+--- a/include/xsimd/arch/xsimd_neon.hpp
++++ b/include/xsimd/arch/xsimd_neon.hpp
+@@ -756,43 +756,6 @@ namespace xsimd
+             store_complex_aligned(dst, src, A {});
+         }
+ 
+-        /*********************
+-         * store<batch_bool> *
+-         *********************/
+-        template <class T, class A, detail::enable_sized_t<T, 1> = 0>
+-        XSIMD_INLINE void store(batch_bool<T, A> b, bool* mem, requires_arch<neon>) noexcept
+-        {
+-            uint8x16_t val = vshrq_n_u8(b.data, 7);
+-            vst1q_u8((uint8_t*)mem, val);
+-        }
+-
+-        template <class T, class A, detail::enable_sized_t<T, 2> = 0>
+-        XSIMD_INLINE void store(batch_bool<T, A> b, bool* mem, requires_arch<neon>) noexcept
+-        {
+-            uint8x8_t val = vshr_n_u8(vqmovn_u16(b.data), 7);
+-            vst1_u8((uint8_t*)mem, val);
+-        }
+-
+-        template <class T, class A, detail::enable_sized_t<T, 4> = 0>
+-        XSIMD_INLINE void store(batch_bool<T, A> b, bool* mem, requires_arch<neon>) noexcept
+-        {
+-            uint8x8_t val = vshr_n_u8(vqmovn_u16(vcombine_u16(vqmovn_u32(b.data), vdup_n_u16(0))), 7);
+-            vst1_lane_u32((uint32_t*)mem, vreinterpret_u32_u8(val), 0);
+-        }
+-
+-        template <class T, class A, detail::enable_sized_t<T, 8> = 0>
+-        XSIMD_INLINE void store(batch_bool<T, A> b, bool* mem, requires_arch<neon>) noexcept
+-        {
+-            uint8x8_t val = vshr_n_u8(vqmovn_u16(vcombine_u16(vqmovn_u32(vcombine_u32(vqmovn_u64(b.data), vdup_n_u32(0))), vdup_n_u16(0))), 7);
+-            vst1_lane_u16((uint16_t*)mem, vreinterpret_u16_u8(val), 0);
+-        }
+-
+-        template <class A>
+-        XSIMD_INLINE void store(batch_bool<float, A> b, bool* mem, requires_arch<neon>) noexcept
+-        {
+-            store(batch_bool<uint32_t, A>(b.data), mem, A {});
+-        }
+-
+         /*******
+          * neg *
+          *******/
+diff --git a/include/xsimd/arch/xsimd_neon64.hpp b/include/xsimd/arch/xsimd_neon64.hpp
+index 9f3c4bc..04eb51b 100644
+--- a/include/xsimd/arch/xsimd_neon64.hpp
++++ b/include/xsimd/arch/xsimd_neon64.hpp
+@@ -178,16 +178,6 @@ namespace xsimd
+             return store_aligned<A>(dst, src, A {});
+         }
+ 
+-        /*********************
+-         * store<batch_bool> *
+-         *********************/
+-
+-        template <class A>
+-        XSIMD_INLINE void store(batch_bool<double, A> b, bool* mem, requires_arch<neon>) noexcept
+-        {
+-            store(batch_bool<uint64_t, A>(b.data), mem, A {});
+-        }
+-
+         /****************
+          * load_complex *
+          ****************/
+-- 
+2.52.0
+

0002-Fix-detection-of-SSE-AVX-AVX512-when-they-are-explic.patch

@@ -1,147 +0,0 @@
-From c2974c874e14557490eab76d2eebf9f8b9eb88f1 Mon Sep 17 00:00:00 2001
-From: Dmitry Kazakov <dimula73@gmail.com>
-Date: Tue, 28 May 2024 22:21:08 +0200
-Subject: [PATCH 2/2] Fix detection of SSE/AVX/AVX512 when they are explicitly
- disabled by OS
-
-Some CPU vulnerability mitigations may disable AVX functionality
-on the hardware level via the XCR0 register. We should check that
-manually to verify that OS actually allows us to use this feature.
-
-See https://bugs.kde.org/show_bug.cgi?id=484622
-
-Fix #1025
----
- include/xsimd/config/xsimd_cpuid.hpp | 91 ++++++++++++++++++++++------
- 1 file changed, 72 insertions(+), 19 deletions(-)
-
-diff --git a/include/xsimd/config/xsimd_cpuid.hpp b/include/xsimd/config/xsimd_cpuid.hpp
-index 30a9da2..8021fce 100644
---- a/include/xsimd/config/xsimd_cpuid.hpp
-+++ b/include/xsimd/config/xsimd_cpuid.hpp
-@@ -122,6 +122,35 @@ namespace xsimd
- #endif
- 
- #elif defined(__x86_64__) || defined(__i386__) || defined(_M_AMD64) || defined(_M_IX86)
-+
-+                auto get_xcr0_low = []() noexcept
-+                {
-+                    uint32_t xcr0;
-+
-+#if defined(_MSC_VER) && _MSC_VER >= 1400
-+
-+                    xcr0 = (uint32_t)_xgetbv(0);
-+
-+#elif defined(__GNUC__)
-+
-+                    __asm__(
-+                        "xorl %%ecx, %%ecx\n"
-+                        "xgetbv\n"
-+                        : "=a"(xcr0)
-+                        :
-+#if defined(__i386__)
-+                        : "ecx", "edx"
-+#else
-+                        : "rcx", "rdx"
-+#endif
-+                    );
-+
-+#else /* _MSC_VER < 1400 */
-+#error "_MSC_VER < 1400 is not supported"
-+#endif /* _MSC_VER && _MSC_VER >= 1400 */
-+                    return xcr0;
-+                };
-+
-                 auto get_cpuid = [](int reg[4], int level, int count = 0) noexcept
-                 {
- 
-@@ -156,19 +185,43 @@ namespace xsimd
- 
-                 get_cpuid(regs1, 0x1);
- 
--                sse2 = regs1[3] >> 26 & 1;
--                sse3 = regs1[2] >> 0 & 1;
--                ssse3 = regs1[2] >> 9 & 1;
--                sse4_1 = regs1[2] >> 19 & 1;
--                sse4_2 = regs1[2] >> 20 & 1;
--                fma3_sse42 = regs1[2] >> 12 & 1;
-+                // OS can explicitly disable the usage of SSE/AVX extensions
-+                // by setting an appropriate flag in CR0 register
-+                //
-+                // https://docs.kernel.org/admin-guide/hw-vuln/gather_data_sampling.html
-+
-+                unsigned sse_state_os_enabled = 1;
-+                unsigned avx_state_os_enabled = 1;
-+                unsigned avx512_state_os_enabled = 1;
-+
-+                // OSXSAVE: A value of 1 indicates that the OS has set CR4.OSXSAVE[bit
-+                // 18] to enable XSETBV/XGETBV instructions to access XCR0 and
-+                // to support processor extended state management using
-+                // XSAVE/XRSTOR.
-+                bool osxsave = regs1[2] >> 27 & 1;
-+                if (osxsave)
-+                {
-+
-+                    uint32_t xcr0 = get_xcr0_low();
-+
-+                    sse_state_os_enabled = xcr0 >> 1 & 1;
-+                    avx_state_os_enabled = xcr0 >> 2 & sse_state_os_enabled;
-+                    avx512_state_os_enabled = xcr0 >> 6 & avx_state_os_enabled;
-+                }
-+
-+                sse2 = regs1[3] >> 26 & sse_state_os_enabled;
-+                sse3 = regs1[2] >> 0 & sse_state_os_enabled;
-+                ssse3 = regs1[2] >> 9 & sse_state_os_enabled;
-+                sse4_1 = regs1[2] >> 19 & sse_state_os_enabled;
-+                sse4_2 = regs1[2] >> 20 & sse_state_os_enabled;
-+                fma3_sse42 = regs1[2] >> 12 & sse_state_os_enabled;
- 
--                avx = regs1[2] >> 28 & 1;
-+                avx = regs1[2] >> 28 & avx_state_os_enabled;
-                 fma3_avx = avx && fma3_sse42;
- 
-                 int regs8[4];
-                 get_cpuid(regs8, 0x80000001);
--                fma4 = regs8[2] >> 16 & 1;
-+                fma4 = regs8[2] >> 16 & avx_state_os_enabled;
- 
-                 // sse4a = regs[2] >> 6 & 1;
- 
-@@ -176,23 +229,23 @@ namespace xsimd
- 
-                 int regs7[4];
-                 get_cpuid(regs7, 0x7);
--                avx2 = regs7[1] >> 5 & 1;
-+                avx2 = regs7[1] >> 5 & avx_state_os_enabled;
- 
-                 int regs7a[4];
-                 get_cpuid(regs7a, 0x7, 0x1);
--                avxvnni = regs7a[0] >> 4 & 1;
-+                avxvnni = regs7a[0] >> 4 & avx_state_os_enabled;
- 
-                 fma3_avx2 = avx2 && fma3_sse42;
- 
--                avx512f = regs7[1] >> 16 & 1;
--                avx512cd = regs7[1] >> 28 & 1;
--                avx512dq = regs7[1] >> 17 & 1;
--                avx512bw = regs7[1] >> 30 & 1;
--                avx512er = regs7[1] >> 27 & 1;
--                avx512pf = regs7[1] >> 26 & 1;
--                avx512ifma = regs7[1] >> 21 & 1;
--                avx512vbmi = regs7[2] >> 1 & 1;
--                avx512vnni_bw = regs7[2] >> 11 & 1;
-+                avx512f = regs7[1] >> 16 & avx512_state_os_enabled;
-+                avx512cd = regs7[1] >> 28 & avx512_state_os_enabled;
-+                avx512dq = regs7[1] >> 17 & avx512_state_os_enabled;
-+                avx512bw = regs7[1] >> 30 & avx512_state_os_enabled;
-+                avx512er = regs7[1] >> 27 & avx512_state_os_enabled;
-+                avx512pf = regs7[1] >> 26 & avx512_state_os_enabled;
-+                avx512ifma = regs7[1] >> 21 & avx512_state_os_enabled;
-+                avx512vbmi = regs7[2] >> 1 & avx512_state_os_enabled;
-+                avx512vnni_bw = regs7[2] >> 11 & avx512_state_os_enabled;
-                 avx512vnni_vbmi = avx512vbmi && avx512vnni_bw;
- #endif
-             }
--- 
-2.45.2
-

xsimd-13.0.0.tar.gz

@@ -1,3 +0,0 @@
-version https://git-lfs.github.com/spec/v1
-oid sha256:8bdbbad0c3e7afa38d88d0d484d70a1671a1d8aefff03f4223ab2eb6a41110a3
-size 259967

xsimd-14.0.0.tar.gz

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:17de0236954955c10c09d6938d4c5f3a3b92d31be5dadd1d5d09fc1b15490dce
+size 306182

xsimd.changes

@@ -1,3 +1,102 @@
+-------------------------------------------------------------------
+Mon Jan  5 22:05:30 UTC 2026 - Dirk Müller <dmueller@suse.com>
+
+- add 0001-Revert-Extend-1172-approach-to-arm-store-version.patch
+  to fix test failures on aarch64 (gh#xtensor-stack/xsimd#1232)
+
+-------------------------------------------------------------------
+Fri Jan  2 09:26:12 UTC 2026 - Dirk Müller <dmueller@suse.com>
+
+- update to 14.0.0:
+  * New architecture: VMX with VSX extension
+  * [API] Add xsimd::bitwise_[l|r]shift<N>(...) and
+    xsimd::rot[l|r]<N>(...)
+  * [API] Add xsimd::widen to widen a batch to a batch twice as
+    big
+  * [API] Add xsimd::first() function to extract the first lane
+    from a batch
+  * [API] Reorder xsimd::make_batch_constant and
+    xsimd::make_batch_bool_constant template arguments
+  * Bump CMake requirement to 3.10
+  * Provide generic and specialize implementation of
+    xsimd::reduce_mul
+  * Have xsimd::max / min behave as std::max / min when one
+    argument is NaN
+  * Optimize batch_bool load/store from/to array of booleans
+  * Cleaner error when trying to instantiate a batch while no
+    arch is supported
+  * Fix XSIMD_INLINE for compilers that don't have always_inline
+  * Rename xsimd::generic in xsimd::common
+  * Fix xsimd::log10 implementation under -ffast-math, and add
+    -fast-math-support to generic math algorithm and tests
+  * Bump xtl dependency requirement
+  * Provide a generic implementation of swizzle with constant
+    mask
+  * Enable xsimd with only emulated arch
+  * Rename avx512vnni<vbmi> in avx512vnni<vbmi2>
+  * [SSE2] Fix and improve xsimd::swizzle on [u]int16
+  * [AVX512x] Specialize xsimd::insert, xsimd::incr_if,
+    xsimd::decr_if
+  * [AVX512F,AVX512VBMI] Sepcialize xsimd::slide_left and
+    xsimd::slide_right
+  * [AVX512F] Fix batch_bool xor
+  * [WASM] Fix neq for batch_bool
+  * [AVX/AVX2/AVX512/ARM32] Improve implementation of
+    xsimd::swizzle
+  * [AVX512VBMI2] Speciliaze xsimd::compress and xsimd::expand
+  * [SSE/AVX/AVX512] Improve xsimd::reduce_add
+  * [SSSE3/AVX2] Fix xsimd::rotate_left implementation for
+    [u]int16 and optimize the [u]int8 implementation
+  * [AVX2] Fix implementation of xsimd::rotate_left
+  * [AVX512] Disable faulty implementation of xsimd::rotate_left
+  * [ARM64] Improve implementation of comparison operator for 64
+    bit integers
+  * [AVX512BW] Optimize xsimd::shift_left and xsimd::shift_right
+  * [AVX512F] Fix batch_const with 16b and 8b integers
+
+-------------------------------------------------------------------
+Fri Aug  8 23:08:28 UTC 2025 - Eyad Issa <eyadlorenzo@gmail.com>
+
+- Deduplicate files in %install using %fdupes macro
+- Make the -devel and the -doc packages noarch
+
+-------------------------------------------------------------------
+Mon Aug  4 23:49:04 UTC 2025 - Eyad Issa <eyadlorenzo@gmail.com>
+
+- Delete patches (upstreamed):
+  * 0001-Fix-xsimd-available_architectures-.has-for-sve-and-r.patch
+  * 0002-Fix-detection-of-SSE-AVX-AVX512-when-they-are-explic.patch
+- Update to version 13.2.0:
+  * Added broadcast overload for bool
+  * Fixed kernel::store for booleans
+  * Explicitly verify dependency between architectures
+    (like sse2 implies sse2)
+  * Use default arch alignment as default alignment for
+    xsimd::aligned_allocator
+  * sse2 version of xsimd::swizzle on [u]int16_t
+  * avx implementation of transpose for [u]int[8|16]
+  * Implement [u]int8 and [u]int16 matrix transpose for 128 bit
+    registers
+  * Fix fma4 support
+- Update to version 13.1.0:
+  * Fix rotate_left and rotate_right behavior (it was swapped!)
+  * Fix compress implementation on RISC-V
+  * Improve RISC-V CI
+  * Fix clang-17 compilation on RISC-V
+  * Validate cmake integration
+  * Provide xsimd::transpose on 64 and 32 bits on most platforms
+  * Improve documentation
+  * Provide xsimd::batch_bool::count
+  * Fix interaction between xsimd::make_sized_batch_t and
+    xsimd::batch<std::complex, ...>
+  * Fix vbmi, sve and rvv detection through
+    xsimd::available_architectures
+  * Fix compilation on MS targets where small can be defined.
+  * Change default install directory for installed headers.
+  * Support mixed-complex implementations of xsimd::pow()
+  * Improve xsimd::pow implementation for complex numbers
+  * Fix uninitialized read in lgamma implementation
+
 -------------------------------------------------------------------
 Thu Feb 27 13:55:27 UTC 2025 - Jan Engelhardt <jengelh@inai.de>
 
@@ -6,7 +105,7 @@ Thu Feb 27 13:55:27 UTC 2025 - Jan Engelhardt <jengelh@inai.de>
 -------------------------------------------------------------------
 Tue Jan 21 00:57:46 UTC 2025 - Steve Kowalik <steven.kowalik@suse.com>
 
-- Explicitly BuildRequires sphinx_rtd_theme. 
+- Explicitly BuildRequires sphinx_rtd_theme.
 
 -------------------------------------------------------------------
 Tue Aug 27 00:37:55 UTC 2024 - Guang Yee <gyee@suse.com>

xsimd.spec

@@ -1,7 +1,7 @@
 #
 # spec file for package xsimd
 #
-# Copyright (c) 2025 SUSE LLC
+# Copyright (c) 2026 SUSE LLC and contributors
 #
 # All modifications and additions to the file contributed by third parties
 # remain the property of their copyright owners, unless otherwise agreed
@@ -18,21 +18,20 @@
 
 %{?sle15_python_module_pythons}
 Name:           xsimd
-Version:        13.0.0
+Version:        14.0.0
 Release:        0
 Summary:        C++ wrappers for SIMD intrinsics
 License:        BSD-3-Clause
 Group:          Development/Libraries/C and C++
 URL:            https://xsimd.readthedocs.io/en/latest/
 Source0:        https://github.com/xtensor-stack/xsimd/archive/refs/tags/%{version}.tar.gz#/%{name}-%{version}.tar.gz
-# PATCH-FIX-UPSTREAM -- https://mail.kde.org/pipermail/distributions/2024-July/001511.html
-Patch0:         0001-Fix-xsimd-available_architectures-.has-for-sve-and-r.patch
-Patch1:         0002-Fix-detection-of-SSE-AVX-AVX512-when-they-are-explic.patch
+Patch1:         0001-Revert-Extend-1172-approach-to-arm-store-version.patch
 BuildRequires:  %{python_module breathe}
 BuildRequires:  %{python_module sphinx_rtd_theme}
 BuildRequires:  cmake
 BuildRequires:  doctest-devel
 BuildRequires:  doxygen
+BuildRequires:  fdupes
 BuildRequires:  gcc-c++
 BuildRequires:  make
 BuildRequires:  pkgconfig
@@ -68,11 +67,14 @@ common mathematical functions operating on batches.
 mkdir -p %{buildroot}%{_docdir}/%{name}
 cp -r %{_builddir}/%{name}-%{version}/docs/build/html/* %{buildroot}%{_docdir}/%{name}
 
+%fdupes %{buildroot}
+
 %check
 %ctest
 
 %package devel
 Summary:        Development files for xsimd
+BuildArch:      noarch
 
 %description devel
 SIMD (Single Instruction, Multiple Data) is a feature of microprocessors that
@@ -91,12 +93,13 @@ This package contains the developments files needed to use xsimd
 %files devel
 %license LICENSE
 %{_includedir}/xsimd
-%{_libdir}/cmake/xsimd
-%{_libdir}/pkgconfig/xsimd.pc
+%{_datadir}/cmake/xsimd/
+%{_datadir}/pkgconfig/xsimd.pc
 
 %package doc
 Summary:        Documentation for xsimd
 Group:          Documentation/HTML
+BuildArch:      noarch
 
 %description doc
 SIMD (Single Instruction, Multiple Data) is a feature of microprocessors that