forked from pool/binutils
Nicer changelog.
OBS-URL: https://build.opensuse.org/package/show/devel:gcc/binutils?expand=0&rev=473
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Michael Matz
Git OBS Bridge
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@ -2,47 +2,51 @@
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Tue Aug 6 14:09:24 UTC 2024 - Michael Matz <matz@suse.com>
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Tue Aug 6 14:09:24 UTC 2024 - Michael Matz <matz@suse.com>
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- Update to version 2.43:
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- Update to version 2.43:
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* new .base64 pseudo-op, allowing base64 encoded data as strings
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* new .base64 pseudo-op, allowing base64 encoded data as strings
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* Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF
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* Intel APX: add support for CFCMOV, CCMP, CTEST, zero-upper, NF
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(APX_F now fully supported)
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(APX_F now fully supported)
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* x86 Intel syntax now warns about more mnemonic suffixes
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* x86 Intel syntax now warns about more mnemonic suffixes
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* macros and .irp/.irpc/.rept bodies can use \+ to get at number of times
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* macros and .irp/.irpc/.rept bodies can use \+ to get at number
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the macro/body was executed
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of times the macro/body was executed
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* aarch64: support 'armv9.5-a' for -march, add support for LUT and LUT2
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* aarch64: support 'armv9.5-a' for -march, add support for LUT
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* s390: base register operand in D(X,B) and D(L,B) can now be omitted
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and LUT2
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(ala 'D(X,)'); warn when register type doesn't match operand type
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* s390: base register operand in D(X,B) and D(L,B) can now be
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(use option 'warn-regtype-mismatch=[strict|relaxed|no]' to adjust)
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omitted (ala 'D(X,)'); warn when register type doesn't match
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* riscv: support various extensions: Zacas, Zcmp, Zfbfmin, Zvfbfmin,
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operand type (use option
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Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw, XSfCease, all at
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'warn-regtype-mismatch=[strict|relaxed|no]' to adjust)
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version 1.0;
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* riscv: support various extensions: Zacas, Zcmp, Zfbfmin,
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remove support for assembly of privileged spec 1.9.1 (linking support
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Zvfbfmin, Zvfbfwma, Smcsrind/Sscsrind, XCvMem, XCvBi, XCvElw,
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remains)
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XSfCease, all at version 1.0;
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* arm: remove support for some old co-processors: Maverick and FPA
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remove support for assembly of privileged spec 1.9.1 (linking
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* mips: '--trap' now causes either trap or breakpoint instructions to
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support remains)
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be emitted as per current ISA, instead of always using trap insn
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* arm: remove support for some old co-processors: Maverick and FPA
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and failing when current ISA was incompatible with that
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* mips: '--trap' now causes either trap or breakpoint instructions
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* LoongArch: accept .option pseudo-op for fine-grained control
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to be emitted as per current ISA, instead of always using trap
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of assembly code options; add support for DT_RELR
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insn and failing when current ISA was incompatible with that
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* readelf: now displays RELR relocations in full detail;
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* LoongArch: accept .option pseudo-op for fine-grained control
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add -j/--display-section to show just those section(s) content
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of assembly code options; add support for DT_RELR
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according to their type
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* readelf: now displays RELR relocations in full detail;
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* objdump/readelf now dump also .eh_frame_hdr (when present) when
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add -j/--display-section to show just those section(s) content
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dumping .eh_frame
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according to their type
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* gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake processors;
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* objdump/readelf now dump also .eh_frame_hdr (when present) when
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add minimal support for riscv
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dumping .eh_frame
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* linker:
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* gprofng: add event types for AMD Zen3/Zen4 and Intel Ice Lake
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- put .got and .got.plt into relro segment
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processors; add minimal support for riscv
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- add -z isa-level-report=[none|all|needed|used] to the x86 ELF
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* linker:
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linker to report needed and used x86-64 ISA levels
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- put .got and .got.plt into relro segment
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- add --rosegment option which changes the -z separate-code option
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- add -z isa-level-report=[none|all|needed|used] to the x86 ELF
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so that only one read-only segment is created (instead of two)
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linker to report needed and used x86-64 ISA levels
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- add --section-ordering-file <FILE> option to add extra mapping
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- add --rosegment option which changes the -z separate-code
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of input sections to output sections
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option so that only one read-only segment is created (instead
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- add -plugin-save-temps to store plugin intermediate files permanently
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of two)
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* Removed binutils-2.42.tar.bz2, binutils-2.42-branch.diff.gz.
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- add --section-ordering-file <FILE> option to add extra
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* Added binutils-2.43.tar.bz2, binutils-2.43-branch.diff.gz.
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mapping of input sections to output sections
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* Removed upstream patch riscv-no-relax.patch.
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- add -plugin-save-temps to store plugin intermediate files
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* Rebased ld-relro.diff and binutils-revert-rela.diff.
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permanently
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- Removed binutils-2.42.tar.bz2, binutils-2.42-branch.diff.gz.
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- Added binutils-2.43.tar.bz2, binutils-2.43-branch.diff.gz.
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- Removed upstream patch riscv-no-relax.patch.
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- Rebased ld-relro.diff and binutils-revert-rela.diff.
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-------------------------------------------------------------------
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-------------------------------------------------------------------
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Thu Jun 13 08:35:38 UTC 2024 - Andreas Schwab <schwab@suse.de>
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Thu Jun 13 08:35:38 UTC 2024 - Andreas Schwab <schwab@suse.de>
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