2017-04-28 13:47:25 +02:00
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From 28085d5db9376007294f5189c559d3182a2a98f4 Mon Sep 17 00:00:00 2001
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2017-03-15 20:38:55 +01:00
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From: Bruce Rogers <brogers@suse.com>
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Date: Fri, 17 May 2013 16:49:58 -0600
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Subject: [PATCH] increase x86_64 physical bits to 42
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Allow for guests with higher amounts of ram. The current thought
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is that 2TB specified on qemu commandline would be an appropriate
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limit. Note that this requires the next higher bit value since
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the highest address is actually more than 2TB due to the pci
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memory hole.
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Signed-off-by: Bruce Rogers <brogers@suse.com>
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Signed-off-by: Andreas Färber <afaerber@suse.de>
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---
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2017-03-29 06:22:10 +02:00
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target/i386/cpu.h | 2 +-
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2017-03-15 20:38:55 +01:00
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1 file changed, 1 insertion(+), 1 deletion(-)
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2017-03-29 06:22:10 +02:00
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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2017-05-05 17:05:43 +02:00
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index c4602ca80d..81c02c5a3b 100644
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2017-03-29 06:22:10 +02:00
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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2017-04-12 21:10:15 +02:00
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@@ -1488,7 +1488,7 @@ uint64_t cpu_get_tsc(CPUX86State *env);
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2017-03-15 20:38:55 +01:00
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/* XXX: This value should match the one returned by CPUID
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* and in exec.c */
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# if defined(TARGET_X86_64)
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-# define TCG_PHYS_ADDR_BITS 40
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+# define TCG_PHYS_ADDR_BITS 42
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# else
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# define TCG_PHYS_ADDR_BITS 36
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# endif
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